Integrated circuit device

An integrated circuit device comprising:

• a substrate comprising a plurality of active regions spaced apart from each other and a plurality of word line trenches each extending longitudinally in a first horizontal direction across some of the plurality of active regions;
• a plurality of word lines each inside respective ones of the plurality of word line trenches and extending longitudinally in the first horizontal direction at a vertical level lower than a main surface of the substrate;
• a plurality of bit lines extending longitudinally in a second horizontal direction perpendicular to the first horizontal direction on the substrate;
• a plurality of conductive plugs respectively in spaces between each of the plurality of bit lines and electrically connected to one active region of the plurality of active regions;
• and
• a plurality of pad structures between the substrate and the plurality of conductive plugs,
• wherein each of the plurality of pad structures comprises:
• a conductive pad having opposite sidewalls in the second horizontal direction and a bottom surface, the bottom surface being in contact with the main surface of the substrate between a pair of word line trenches of the plurality of word line trenches and adjacent to each other, and the opposite sidewalls extending along an extension line of an inner sidewall of each of the pair of word line trenches, and
• one or more pad spacers in contact with the opposite sidewalls of the conductive pad and protruding beyond the inner sidewall of each of the pair of word line trenches such that the one or more pad spacers vertically overlaps a portion of a word line of the plurality of word lines inside each of the pair of word line trenches.

An integrated circuit device comprising:

• a substrate having a plurality of active regions and a main surface;
• a plurality of word lines buried in the substrate at a vertical level lower than the main surface and extending longitudinally in a first horizontal direction;
• a plurality of gate dielectric layers respectively surrounding the plurality of word lines;
• a plurality of bit lines extending longitudinally in a second horizontal direction perpendicular to the first horizontal direction on the substrate;
• a plurality of direct contacts each between one bit line of the plurality of bit lines and one active region of the plurality of active regions;
• a plurality of conductive plugs each in a space between respective ones of the plurality of bit lines on the substrate;
• and
• a plurality of pad structures respectively between the plurality of active regions and the plurality of conductive plugs and spaced apart from the plurality of direct contacts,
• wherein each of the plurality of pad structures has a first portion in contact with one active region of the plurality of active regions, and a second portion in contact with one conductive plug of the plurality of conductive plugs,
• each of the plurality of pad structures comprises:
• a conductive pad having a bottom surface in contact with the main surface of the substrate and opposite sidewalls in the second horizontal direction;
• and
• one or more pad spacers in contact with the opposite sidewalls of the conductive pad, having a bottom surface with a vertical level equal to or higher than a vertical level of the bottom surface of the conductive pad, and comprising a portion overlapping one gate dielectric layer of the plurality of gate dielectric layers.