Memory devices and methods for forming the same
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsYaqin Liu, Yanhong Wang, Wei Liu
Life of this patent
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Abstract
A memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The vertical transistor is disposed between the bit line and the storage unit along the first direction.
Claims20
A memory device, comprising:
- a memory array comprising:
- a vertical transistor having a first terminal and a second terminal;
- a storage unit having a first end coupled to the first terminal of the vertical transistor;
- and
- a bit line coupled to the second terminal of the vertical transistor;
- and
- a peripheral circuit coupled to the memory array,
- wherein the vertical transistor comprises a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body;
- and
- the vertical transistor is disposed between the bit line and the storage unit along the first direction.
A memory device, comprising:
- a memory array comprising:
- a vertical transistor having a first terminal and a second terminal;
- a storage unit having a first end coupled to the first terminal of the vertical transistor;
- a bit line coupled to the second terminal of the vertical transistor;
- a first redistribution layer disposed at a first side of the memory array;
- and
- a second redistribution layer disposed at a second side of the memory array opposite to the first side, wherein the vertical transistor, the storage unit, and the bit line are disposed between the first redistribution layer and the second redistribution layer;
- and
- a peripheral circuit coupled to the memory array.
A method for forming a memory device, comprising:
- forming a memory array, comprising:
- forming a vertical transistor on a first substrate;
- forming a storage unit on a first end of the vertical transistor;
- and
- forming a first redistribution layer on the storage unit;
- forming a peripheral circuit on a second substrate;
- bonding the memory array and the peripheral circuit;
- removing the first substrate;
- and
- forming a bit line on a second end of the vertical transistor coupling the first redistribution layer.
Dependencies are inferred from the claim text.