Semiconductor structure, method for manufacturing semiconductor structure, and memory

A memory, comprising one or more semiconductor structures, each semiconductor structure comprising a substrate, a plurality of active pillars arranged above the substrate, a storage structure, and a plurality of transistors,

• wherein the plurality of active pillars are arranged in an array in a first direction and in a second direction, each of the plurality of active pillars comprises a first sub active pillar and a second sub active pillar arranged on the first sub active pillar, the first direction and the second direction intersect with each other and are both parallel to a top surface of the substrate, a material of the first sub active pillar comprises a first element, and resistivity of the first sub active pillar comprising the first element is less than resistivity of the first sub active pillar absence of the first element;
• wherein the storage structure covers a sidewall of the first sub active pillar;
• and
• wherein a channel structure of each of the plurality of transistors is arranged in the second sub active pillar, and an extending direction of the channel structure is the same as an extending direction of the second sub active pillar.

A method for manufacturing a semiconductor structure, comprising:

• providing a substrate, and forming, on the substrate, a plurality of active pillars arranged in an array in a first direction and in a second direction, wherein each of the plurality of active pillars comprises a first sub active pillar and a second sub active pillar arranged on the first sub active pillar, and the first direction and the second direction intersect with each other and are both parallel to a top surface of the substrate;
• adding a first element into the first sub active pillar, wherein resistivity of the first sub active pillar comprising the first element is less than resistivity of the first sub active pillar absence of the first element;
• forming a storage structure at least on a sidewall of the first sub active pillar;
• and
• forming a plurality of transistors, wherein a channel structure of each of the plurality of transistors is arranged in the second sub active pillar, and an extending direction of the channel structure is the same as an extending direction of the second sub active pillar.