Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsJungmin PARK, Hanjin LIM, Hyungsuk JUNG
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Abstract
A semiconductor device including a substrate, a plurality of lower electrodes on the substrate, a dielectric layer stack covering the lower electrodes, and an upper electrode covering the dielectric layer stack may be provided. The dielectric layer stack may include a first dielectric layer on the plurality of lower electrodes, the first dielectric layer including a material having anti-ferroelectricity or paraelectricity, and a second dielectric layer between the first dielectric layer and the upper electrode, the second dielectric layer including a material having ferroelectricity. The upper electrode may include a first upper electrode layer including an N-type impurity.
Claims20
A semiconductor device comprising:
- a substrate;
- a plurality of lower electrodes on the substrate;
- a dielectric layer stack covering the lower electrodes;
- and
- an upper electrode covering the dielectric layer stack,
- wherein the dielectric layer stack includes,
- a first dielectric layer being on the plurality of lower electrodes, the first dielectric layer including a material having anti-ferroelectricity or paraelectricity, and
- a second dielectric layer between the first dielectric layer and the upper electrode, the second dielectric layer including a material having ferroelectricity, and
- wherein the upper electrode includes a first upper electrode layer including an N-type impurity.
A semiconductor device comprising:
- a substrate;
- a plurality of lower electrodes on the substrate;
- a dielectric layer stack covering the plurality of lower electrodes, the dielectric layer stack including a plurality of dielectric layers;
- and
- an upper electrode covering the dielectric layer stack, the upper electrode including a first metal having a first valence,
- wherein the dielectric layer stack includes a ferroelectric layer more adjacent to the upper electrode than to the lower electrodes, the ferroelectric layer having a thickness of about 5 Å to about 20 Å, and
- the upper electrode includes a first upper electrode layer including the first metal and a second metal having a second valence greater than the first valence.
A semiconductor device comprising:
- an isolation layer defining active regions on a substrate;
- gate electrodes crossing the active regions and extending into the isolation layer;
- first impurity regions and second impurity regions in the active regions and a pair of one of the first impurity regions and one of the second impurity regions adjacent to the one of the first impurity regions being on opposite sides of a corresponding one of the gate electrodes;
- bit lines over the gate electrodes and connected to the first impurity regions;
- conductive patterns on side surfaces of the bit lines and connected to the second impurity regions;
- a plurality of lower electrodes vertically extending on the conductive patterns and connected to the conductive patterns, respectively;
- at least one supporter layer spaced apart from an upper surface of the substrate in a vertical direction, extending in a direction parallel to the upper surface of the substrate, and being in contact with a side surface of the plurality of lower electrodes adjacent thereto;
- a first dielectric layer covering the lower electrodes and the supporter layer, the first dielectric layer including a material having anti-ferroelectricity or paraelectricity;
- a second dielectric layer covering the first dielectric layer, the second dielectric layer including a material having ferroelectricity;
- and
- an upper electrode covering the second dielectric layer, the upper electrode including a first upper electrode layer including an N-type impurity.
Dependencies are inferred from the claim text.