Bit Cell for Static Random Access Memory

A method for forming a bit cell for a Static Random-Access Memory (SRAM) that comprises forming, on a semiconductor substrate, a first set of transistors and a second set of transistors, each set of transistors including a respective pass-gate transistor and a respective stacked, complementary transistor pair of an upper transistor and a lower transistor;

• wherein each transistor of the first set comprises a semiconductor channel extending between respective source and drain regions along a horizontal first channel track, and each transistor of the second set comprises a semiconductor channel extending between respective source and drain regions along a horizontal second channel track;
• wherein forming the first and second sets of transistors comprises forming the lower transistors such that they include semiconductor channels located at a first level above the substrate, forming the upper transistors such that they include semiconductor channels at a second level, above the first level, and forming the pass-gate transistors such that they include semiconductor channels at the first level or the second level;
• connecting a source or drain terminal of the lower transistor of each set of transistors to a respective first power supply extending in a first power supply track arranged below the lower transistor;
• and
• connecting a source or drain terminal of the upper transistor of each set of transistors to a respective second power supply extending in a second power supply track arranged above the upper transistor.

A bit cell for a Static Random-Access Memory (SRAM), the bit cell comprising:

• first and second sets of transistors arranged on a substrate, each set comprising a respective pass-gate transistor and a respective stacked complementary transistor pair of an upper transistor and a lower transistor;
• wherein each transistor of the first set comprises a semiconductor channel extending between respective source and drain regions along a horizontal first channel track, and each transistor of the second set comprises a semiconductor channel extending between respective source and drain regions along a horizontal second channel track;
• wherein the semiconductor channels of the lower transistors are arranged at a first level above the substrate and the semiconductor channels of the upper transistors are arranged at a second level, above the first level;
• wherein the semiconductor channels of the pass-gate transistors are arranged at the first level or the second level;
• wherein a source or drain terminal of the lower transistor of each set of transistors is connected to a respective first power supply extending in a first power supply track arranged below the lower transistor;
• wherein a source or drain terminal of the upper transistor of each set of transistors is connected to a respective second power supply extending in a second power supply track arranged above the upper transistor;
• wherein a gate of each of the pass-gate transistors is connected to a respective word line extending in a word line track arranged at the same vertical level as the second power supply track
• wherein a source or drain terminal of the pass-gate transistor of the first set of transistors is connected to a first bit line;
• wherein a source or drain terminal of the pass gate transistor of the second set of transistors is connected to a second bit line;
• and
• wherein the first and second bit lines extend in a respective bit line track arranged at a level between the pass-gate transistors and the word line tracks;
• and
• a first inverter gate electrode forming a common gate electrode for the semiconductor channels of the complementary transistor pair of the first set of transistors and a second inverter gate electrode forming a common gate electrode for the semiconductor channels of the complementary transistor pair of the second set of transistors, wherein the first and second inverter gate electrodes extend in a horizontal gate track transverse to the channel tracks:
• a first pass gate electrode forming a gate of the first pass-gate transistor and being aligned with the first inverter gate electrode;
• a second pass gate electrode forming a gate of the second pass-gate transistor and being aligned with the second inverter gate electrode;
• and
• a dielectric wall disposed in a trench that separates the first pass gate electrode from the first inverter gate electrode and that separates the second pass gate electrode from the second inverter gate electrode.