Eight-transistor static random access memory, layout thereof, and method for manufacturing the same

A method for manufacturing a semiconductor device, comprising:

• forming a plurality of fins over a substrate extending in a first direction and arranged along a second direction, wherein the second direction is perpendicular to the first direction;
• forming a photoresist layer over the plurality of fins;
• patterning the photoresist layer, wherein remaining photoresist layer covers a first fin of the plurality of fins and a second fin of the plurality of fins;
• implanting a dopant in a third fin of the plurality of fins and a fourth fin of the plurality of fins;
• removing the remaining photoresist layer;
• forming one or more work function adjustment layers over a channel region of one or more fins of the plurality of fins, wherein the work function adjustment layers extend in the second direction along a first line;
• forming a first plurality of gate electrode layers the one or more work function adjustment layers, wherein each of the first plurality of gate electrode layers are spaced apart from each other and extend in the second direction along the first line;
• and
• forming a second plurality of gate electrode layers disposed over a channel region of one or more fins of the plurality of fins, wherein each of the second plurality of gate electrode layers are spaced apart from each other and extend in the second direction along a second line, and the second line is substantially parallel to the first line,
• wherein a first gate electrode layer of the first plurality of gate electrodes is disposed over the second fin, the third fin, and the fourth fin,
• the first gate electrode layer includes a first section disposed over the second fin, a second section disposed over the third fin, and a third section disposed over the fourth fin,
• each of the first section, second section, and third section includes one or more of the work function adjustment layers, and
• the number of work function adjustment layers, the thickness of one or more work function adjustment layers, or the material of one or more work function adjustment layers is different in each of the first section, second section, and third section.

A method for manufacturing a semiconductor device, comprising:

• forming a plurality of fins over a substrate extending in a first direction and arranged along a second direction, wherein the second direction is perpendicular to the first direction;
• forming a photoresist layer over the plurality of fins;
• patterning the photoresist layer, wherein remaining photoresist layer covers a first fin of the plurality of fins and a second fin of the plurality of fins;
• implanting a dopant into a first region of the substrate not covered by the remaining photoresist layer to form a counter doped region;
• removing the remaining photoresist layer;
• forming a first plurality of gate electrode layers over a channel region of one or more fins of the plurality of fins, wherein each of the first plurality of gate electrode layers are spaced apart from each other and extend in the second direction along a first line;
• and
• forming a second plurality of gate electrode layers over a channel region of one or more fins of the plurality of fins, wherein each of the second plurality of gate electrode layers are spaced apart from each other and extend in the second direction along a second line, and the second line is substantially parallel to the first line,
• wherein the gate electrode layers are disposed over channel regions of the plurality of fins,
• a first gate electrode layer of the first plurality of gate electrodes is disposed over a first fin, a second fin, and a third fin,
• the first fin is disposed over a second region of the substrate that is not counter doped,
• the second fin and third fin are disposed over the counter doped region of the substrate,
• a distance along the second direction between the first fin and the second fin is S0,
• a distance along the second direction between the second fin and an adjacent boundary of the counter doped region of the substrate is S1, and
• S0 and S1 satisfy 0.4≤S1/S0≤0.5.