Image sensor and operating method thereof
AssigneeSK hynix Inc.
InventorsSun Young LEE, Jeong Eun SONG, Min Seok SHIN
Life of this patent
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Abstract
Disclosed is an image sensor including a plurality of selection circuits each suitable for receiving two clock signals among an input clock signal and a plurality of delayed clock signals, and outputting, as each of a plurality of selection clock signals, one selection clock signal between the two clock signals on the basis of a control signal; and a plurality of buffer circuits suitable for generating the plurality of delayed clock signals on the basis of the plurality of selection clock signals outputted from the plurality of selection circuits.
Claims18
An image sensor comprising:
- a plurality of selection circuits each suitable for receiving two clock signals among an input clock signal and a plurality of delayed clock signals, and outputting, as each of a plurality of selection clock signals, one selection clock signal between the two clock signals on the basis of a control signal;
- and
- a plurality of buffer circuits suitable for generating the plurality of delayed clock signals on the basis of the plurality of selection clock signals outputted from the plurality of selection circuits.
An image sensor comprising:
- a first selection circuit suitable for receiving a first input clock signal and a second delayed clock signal, and outputting, as a first selection clock signal, one of the first input clock signal and the second delayed clock signal on the basis of a control signal;
- a first buffer circuit suitable for generating a first delayed dock signal on the basis of the first selection clock signal;
- a second selection circuit suitable for receiving the first delayed dock signal and a third delayed clock signal, and outputting, as a second selection clock signal, one of the first delayed clock signal and the third delayed clock signal on the basis of the control signal;
- a second buffer circuit suitable for generating the second delayed clock signal on the basis of the second selection clock signal;
- a third selection circuit suitable for receiving the second delayed clock signal and the first input clock signal, and outputting, as a third selection clock signal, one of the second delayed clock signal and the first input clock signal on the basis of the control signal;
- and
- a third buffer circuit suitable for generating the third delayed clock signal on the basis of the third selection clock signal.
An operating method of an image sensor, comprising:
- sequentially generating a plurality of delayed dock signals from a first one to a last one of the delayed clock signals along a forward path of a clock chain on the basis of a control signal during a first exposure period included in a first phase, while keeping the control signal to a first logic level during the first exposure period;
- and
- sequentially generating the plurality of delayed clock signals from the last one to the first one of the delayed clock signals along a backward path of the clock chain on the basis of the control signal during a second exposure period included in a second phase, while keeping the control signal to a second logic level during the second exposure period.
An image sensor for generating depth map information according to a time of flight (TOF) scheme, the image sensor comprising:
- a pixel array configured to generate, from an incident light, pixel signals for the depth information according to a group of output clock signals during first and second exposure periods;
- and
- a controller configured to generate the group based on a forward sequence of delayed clock signals during the first exposure period and based on a backward sequence of the delayed clock signals during the second exposure period,
- wherein the controller includes a chain of delay units, two at both ends of which are configured to selectively receive an input clock signal, and
- wherein the controller is further configured to:
- sequentially generate, based on the input clock signal provided through one of the ends, the forward sequence from a first one to a last one of the delayed clocks signals, and
- sequentially generate, based on the input clock signal provided through the other one of the ends, the backward sequence from the last one to first one of the delayed clocks signals.
Dependencies are inferred from the claim text.