Multi-channel digital isolator with integrated configurable pulse width modulation interlock protection

An apparatus, comprising:

• a digital isolator comprising:
• a first transmitter having a first transmitter output;
• a first receiver having a first receiver input and a first receiver output;
• a second transmitter having a second transmitter output;
• a second receiver having a second receiver input and a second receiver output;
• an isolation barrier coupled between the first transmitter output and the first receiver input and between the second transmitter output and second receiver input, the first transmitter configured to transmit a first input signal across the isolation barrier, and the second transmitter configured to transmit a second input signal across the isolation barrier;
• and
• a first output buffer having a first buffer input, the first output buffer configured to output a first isolated signal;
• and
• a second output buffer having a second buffer input, the second output buffer configured to output a second isolated signal;
• and
• an interlock circuit having a first input coupled to the first receiver output, a second input coupled to the second receiver output, a first output coupled to the first buffer input, and a second output coupled to the second buffer input, wherein the interlock circuit is configured to prevent overlapping active states between the first and second isolated signals.

A digital isolator having a complementary pair channel, comprising:

• a first channel comprising:
• a first receiver having a first receiver output and configured to receive a first input signal across an isolation barrier;
• and
• a first output buffer having a first buffer input and configured to output a first isolated signal;
• and
• a second channel comprising:
• a second receiver having a second receiver output and configured to receive a second input signal across the isolation barrier;
• and
• a second output buffer having a second buffer input and configured to output a second isolated signal;
• and
• an interlock module having a first input coupled to the first receiver output, a second input coupled to the second receiver output, a first output coupled to the first buffer input, and a second output coupled to the second buffer input, the interlock module configured to prevent overlapping active states between the first and second isolated signals.

A motor driver having an output adapted to be coupled to a motor, the motor driver comprising:

• first circuitry having a first output and adapted to be coupled to a first voltage supply;
• second circuitry having a first input, a second input and a second output adapted to be coupled to the motor, the second circuitry adapted to be coupled to a second voltage supply that is greater than the first voltage supply;
• an isolation barrier connected between the first circuitry and the second circuitry thereby isolating the first circuitry from the second circuitry;
• and
• wherein the second circuitry includes:
• an interlock circuit having a third input coupled to the first input, a fourth input coupled to the second input, a third output and a fourth output;
• a first buffer circuit having a fifth input coupled to the third output and having a fifth output coupled to the interlock circuit;
• a second buffer circuit having a sixth input coupled to the fourth output and having a sixth output coupled to the interlock circuit;
• and
• wherein a signal at the fifth output is asserted only if a signal at the sixth output is de-asserted.