# US 2023/0411537 A1 · Semiconductor devices and methods for increased capacitance

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- Number: US 2023/0411537 A1
- Document ID: US20230411537A1
- Status: Published application
- Kind: A1
- Application number: 18/226,888
- Filed: 2023-07-27
- Published: 2023-12-21
- Earliest claimed: 2022-03-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd
- Inventors: Cheng-You Tai; Sung-Hsin Yang; Tsung Jing Wu; Jung-Chi Jeng; Ling-Sung Wang; Ru-Shang Hsiao
- Web page: https://patentgrep.com/patent/US20230411537A1

## CPC

- H10D 1/66: Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
- H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10D 1/716: {having vertical extensions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices having increased capacitance without increased fin height or increased chip area are disclosed. Grooves are formed across a width of the fin(s) to increase the overlapping surface area with the gate terminal, in particular with a length of the groove being less than or equal to the fin width. Methods of forming such grooved fins and semiconductor capacitor devices are also described.

## Claims

### Claim 1

A method for forming a semiconductor capacitor device, comprising:
receiving a substrate with at least one fin;
applying a mask with a pattern across a width of the at least one fin; and
etching the at least one fin to form at least a first groove across the width of the at least one fin;
removing the mask; and
forming a first gate stack in the first groove of the at least one fin.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first groove has a length that is less than or equal to the width of the at least one fin.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first groove has a depth that is deeper or shallower than a height of the at least one fin.

### Claim 4 (depends on 1)

The method of claim 1, wherein in a longitudinal side cross-sectional view, the first groove has a triangular or trapezoidal or rectangular shape.

### Claim 5 (depends on 1)

The method of claim 1, wherein the at least one fin further comprises a second groove across the width of the at least one fin.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first groove and the second groove each include an STI layer, wherein the depths of the STI layers differ from each other.

### Claim 7 (depends on 5)

The method of claim 5, wherein the first groove and the second groove have different depths.

### Claim 8 (depends on 1)

The method of claim 1, wherein the at least one fin passes through a capacitor region and a normal region, and the first groove is in the capacitor region; and wherein a second gate stack is formed in the normal region which is electrically isolated from the first gate stack.

### Claim 9 (depends on 1)

The method of claim 1, further comprising implanting ions into the at least one fin prior to forming the first gate stack.

### Claim 10 (depends on 1)

The method of claim 1, further comprising forming an STI layer in the first groove prior to forming the first gate stack.

### Claim 11 (depends on 1)

The method of claim 1, further comprising forming gate spacers adjacent the first gate stack.

### Claim 12 (depends on 11)

The method of claim 11, further comprising forming a dielectric layer adjacent the gate spacers.

### Claim 13 (depends on 12)

The method of claim 12, further comprising forming an insulation layer over the gate stack.

### Claim 14 (depends on 13)

The method of claim 13, further comprising forming electrical contacts through the insulation layer and the dielectric layer to the at least fin.

### Claim 15

A method for forming a semiconductor capacitor device, comprising:
applying a first mask with a pattern to a substrate, wherein the first mask pattern comprises a spacer line that includes at least one gap, wherein a length of each gap is less than or equal to a width of the spacer line;
etching the substrate to form a fin with at least one groove across the width of the fin; and
removing the first mask.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
depositing an STI layer;
etching the STI layer so that the fin is exposed;
applying a second mask that exposes the at least one groove;
etching the STI layer so that the STI layer in the at least one groove is shallower than the STI layer at the ends of the fin; and
removing the second mask.

### Claim 17

A method for forming a semiconductor device that includes two separate transistors having different capacitances, comprising:
receiving a substrate having at least one fin that extends across a capacitor region and a normal region;
depositing an STI layer over the fin;
applying a mask to the normal region;
etching the STI layer such that a depth of the STI layer in the capacitor region is different from a depth of the STI layer in the normal region;
forming a first gate stack over the fin in the capacitor region;
forming a second gate stack over the fin in the normal region;
depositing a dielectric layer between the first gate stack and the second gate stack to obtain the two separate transistors having different capacitances.

### Claim 18 (depends on 17)

The method of claim 17, wherein at least one groove is present in the fin in both the capacitor region and the normal region.

### Claim 19 (depends on 18)

The method of claim 18, wherein a surface area of the at least one groove in the capacitor region is different from a surface area of the at least one groove in the normal region.

### Claim 20 (depends on 17)

The method of claim 17, wherein a gate oxide layer of the first gate stack is different from a gate oxide layer of the second gate stack.