# US 2023/0411531 A1 · Gate-all-around transistors with hybrid orientation

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- Number: US 2023/0411531 A1
- Document ID: US20230411531A1
- Status: Published application
- Kind: A1
- Application number: 17/807,945
- Filed: 2022-06-21
- Published: 2023-12-21
- Earliest claimed: 2022-06-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Nicolas Jean Loubet; Shogo Mochizuki; Maruf Amin Bhuiyan
- Web page: https://patentgrep.com/patent/US20230411531A1

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/364: {of IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a p-type field-effect transistor including first channels made of silicon having a (110) crystallographic orientation. The semiconductor device further includes an n-type field-effect transistor including second channels made of silicon having a (100) crystallographic orientation. The semiconductor device further includes a gate surrounding the first channels and the second channels.

## Claims

### Claim 1

A semiconductor device, comprising:
a p-type field-effect transistor including first channels made of silicon having a (110) crystallographic orientation;
an n-type field-effect transistor including second channels made of silicon having a (100) crystallographic orientation; and
a gate surrounding the first channels and the second channels.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
the p-type field-effect transistor and the n-type field-effect transistor are arranged on the same silicon substrate.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein:
the silicon substrate has a (110) crystallographic orientation.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein:
the silicon substrate has a (100) crystallographic orientation.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein:
each of the first channels is a first silicon sheet;
each of the second channels is a second silicon sheet; and
the p-type field-effect transistor includes a number of first silicon sheets that is different than a number of second silicon sheets included in the n-type field effect transistor.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein:
a thickness of each of the first silicon sheets is different than a thickness of each of the second silicon sheets.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein:
each of the first silicon sheets is included in a p-type stack;
each of the second silicon sheets is included in an n-type stack; and
an uppermost surface of the p-type stack is substantially coplanar with an uppermost surface of the n-type stack.

### Claim 8 (depends on 5)

The semiconductor device of claim 5, further comprising:
a separation layer separating at least one of the p-type stack or the n-type stack from a silicon substrate.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein:
the separation layer includes a bonding interface formed within the separation layer.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, further comprising:
a further separation layer separating the n-type stack from the silicon substrate, wherein:
the separation layer separates the p-type stack from the silicon substrate; and
the further separation layer is made of a different material than the separation layer.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein:
the separation layer includes a bonding interface formed between the separation layer and the silicon substrate.

### Claim 12

A method for making a semiconductor device, the method comprising:
bonding a first wafer including a first silicon substrate having a first crystallographic orientation to a second wafer including a second silicon substrate having a second crystallographic orientation;
removing the second silicon substrate;
removing a portion of a stack of alternating silicon layers and silicon germanium layers from the second wafer, wherein each of the silicon layers has the second crystallographic orientation; and
forming a further stack of alternating further silicon layers and further silicon germanium layers on the first wafer, wherein each of the further silicon layers has the first crystallographic orientation.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
forming a p-type field-effect transistor including the silicon layers as p-type channels; and
forming an n-type field-effect transistor including the further silicon layers as n-type channels.

### Claim 14 (depends on 13)

The method of claim 13, wherein:
forming the p-type field-effect transistor and forming the n-type field-effect transistor includes forming a gate surrounding the p-type channels and the n-type channels.

### Claim 15 (depends on 12)

The method of claim 12, wherein:
removing the portion of the stack includes exposing a portion of an uppermost surface of the first wafer.

### Claim 16 (depends on 15)

The method of claim 15, wherein:
forming the further stack includes epitaxially growing the alternating further silicon layers and further silicon germanium layers on the exposed portion of the uppermost surface of the first wafer.

### Claim 17

A method of forming a semiconductor device, the method comprising:
forming a p-type field-effect transistor including channels having a first crystallographic orientation on a first wafer; and
forming an n-type field-effect transistor including channels having a second crystallographic orientation on the first wafer, wherein:
the first crystallographic orientation is different than the second crystallographic orientation; and
forming the p-type field-effect transistor and forming the n-type field-effect transistor includes forming a gate surrounding the channels having the first crystallographic orientation and the channels having the second crystallographic orientation.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
forming the p-type field-effect transistor and forming the n-type field-effect transistor includes bonding a second wafer to the first wafer;
the first wafer includes a silicon substrate having one of the first crystallographic orientation or the second crystallographic orientation; and
the second wafer includes a silicon substrate having the other of the first crystallographic orientation or the second crystallographic orientation.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
the second wafer includes a stack of alternating silicon layers and silicon germanium layers;
all of the silicon layers have one of the first crystallographic orientation or the second crystallographic orientation; and
all of the silicon layers have the same one of the first crystallographic orientation or the second crystallographic orientation.

### Claim 20 (depends on 19)

The method of claim 19, wherein:
forming one of the p-type field-effect transistor or the n-type field-effect transistor includes epitaxially growing a stack of alternating further silicon layers and further silicon germanium layers on the first wafer;
all of the further silicon layers have the same crystallographic orientation as the first wafer; and
all of the further silicon layers have the other of the first crystallographic orientation or the second crystallographic orientation than the silicon layers.