# US 2023/0411527 A1 · Semiconductor device and manufacturing method thereof

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- Number: US 2023/0411527 A1
- Document ID: US20230411527A1
- Status: Published application
- Kind: A1
- Application number: 17/843,835
- Filed: 2022-06-17
- Published: 2023-12-21
- Earliest claimed: 2022-06-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shih-Cheng CHEN; Zhi-Chang LIN; Jung-Hung CHANG; Chien Ning YAO; Tsung-Han CHUANG; Kai-Lin CHUANG; Kuo-Cheng CHIANG
- Web page: https://patentgrep.com/patent/US20230411527A1

## CPC

- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10P 14/3462: {Nanowires}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/364: {of IGFETs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a sidewall spacer. The channel layer is over a substrate. The gate structure wraps around the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer. The sidewall spacer is on a sidewall of the first source/drain epitaxial structure and includes a first dielectric layer and a second dielectric layer over the first dielectric layer and in contact with first source/drain epitaxial structure. The first dielectric layer and the second dielectric layer include different materials.

## Claims

### Claim 1

A device comprising:
a channel layer over a substrate;
a gate structure wrapping around the channel layer;
a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite sides of the channel layer; and
a sidewall spacer on a sidewall of the first source/drain epitaxial structure, wherein the sidewall spacer comprises:
a first dielectric layer; and
a second dielectric layer over the first dielectric layer and in contact with first source/drain epitaxial structure, wherein the first dielectric layer and the second dielectric layer comprise different materials.

### Claim 2 (depends on 1)

The device of claim 1, wherein a topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first source/drain epitaxial structure is in contact with a topmost surface of the second dielectric layer.

### Claim 4 (depends on 1)

The device of claim 1, wherein a width of the first dielectric layer is greater than a width of the second dielectric layer.

### Claim 5 (depends on 1)

The device of claim 1, wherein a difference between widths of the first dielectric layer and the second dielectric layer is in a range of about 1 nm to about 10 nm.

### Claim 6 (depends on 1)

The device of claim 1, wherein the first source/drain epitaxial structure is spaced apart from the first dielectric layer.

### Claim 7 (depends on 1)

The device of claim 1, further comprising a contact etch stop layer in contact with the first dielectric layer and the second dielectric layer of the sidewall spacer.

### Claim 8

A device comprising:
a gate structure over a substrate;
a nanostructure embedded in the gate structure;
a first top source/drain structure and a second top source/drain structure connected to the nanostructure and on opposite sides of the gate structure;
a sidewall spacer adjacent to the first top source/drain structure and comprising:
a bottom dielectric layer; and
a top dielectric layer over the bottom dielectric layer; and
a spacer residue between the sidewall spacer and the first top source/drain structure, wherein the spacer residue is directly over the bottom dielectric layer.

### Claim 9 (depends on 8)

The device of claim 8, wherein the spacer residue is in contact with an inner sidewall of the top dielectric layer of the sidewall spacer.

### Claim 10 (depends on 8)

The device of claim 8, wherein the first top source/drain structure is in contact with an inner sidewall of the top dielectric layer of the sidewall spacer.

### Claim 11 (depends on 8)

The device of claim 8, wherein a vertical thickness of the spacer residue is smaller than a vertical thickness of the sidewall spacer.

### Claim 12 (depends on 8)

The device of claim 8, further comprising an inner spacer between the gate structure and the first top source/drain structure.

### Claim 13 (depends on 12)

The device of claim 12, wherein the inner spacer and the spacer residue comprise the same material.

### Claim 14 (depends on 8)

The device of claim 8, further comprising a bottom source/drain structure between the first top source/drain structure and the substrate, wherein the bottom source/drain structure is in contact with a concave surface of the bottom dielectric layer.

### Claim 15

A method comprising:
forming a fin structure over a substrate, wherein the fin structure comprises a sacrificial layer and a channel layer over the sacrificial layer;
forming a dummy gate structure over the fin structure;
forming a sidewall spacer on a sidewall of the fin structure, wherein the sidewall spacer comprises a first dielectric layer and a second dielectric layer outside the first dielectric layer;
removing a portion of the fin structure such that a remaining portion of the fin structure is under the dummy gate structure;
etching back the first dielectric layer of the sidewall spacer such that the second dielectric layer of the sidewall spacer protrudes from the first dielectric layer;
epitaxially growing a source/drain structure over the substrate and in contact with the channel layer of the remaining portion of the fin structure; and
replacing the dummy gate structure and the sacrificial layer with a metal gate structure.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
after etching back the first dielectric layer of the sidewall spacer, recessing the sacrificial layer of the remaining portion of the fin structure; and
forming an inner spacer on a sidewall of the recessed sacrificial layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein during forming the inner spacer on the sidewall of the recessed sacrificial layer, a spacer residue of the inner spacer is formed on an inner sidewall of the second dielectric layer of the sidewall spacer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the spacer residue is spaced apart from the channel layer of the remaining portion of the fin structure.

### Claim 19 (depends on 15)

The method of claim 15, wherein a nitrogen concentration of the second dielectric layer is higher than a nitrogen concentration of the first dielectric layer.

### Claim 20 (depends on 15)

The method of claim 15, further comprising forming a gate spacer on a sidewall of the dummy gate structure during forming the sidewall spacer.