# US 2023/0411468 A1 · Semiconductor structure

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- Number: US 2023/0411468 A1
- Document ID: US20230411468A1
- Status: Published application
- Kind: A1
- Application number: 17/843,815
- Filed: 2022-06-17
- Published: 2023-12-21
- Earliest claimed: 2022-06-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jhon-Jhy LIAW
- Web page: https://patentgrep.com/patent/US20230411468A1

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/503: {having non-rectangular cross-sections}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10W 20/427: {Power or ground buses}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor structure includes a circuit cell having transistors. Each of the transistors includes nanostructures vertically stacked from each other, and a gate structure wrapped around the nanostructures and extending in a first direction. The semiconductor structure further includes a dielectric gate structure extending in the first direction and adjacent to the circuit cell in a second direction. The second direction is perpendicular to the first direction. The semiconductor structure further includes a first source/drain feature between adjacent two of the gate structures, a second source/drain feature between one of the gate structures and the dielectric gate structure, a first source/drain contact over the first source/drain feature and having a first width in the second direction, and a second source/drain contact over the second source/drain feature and having a second width in the second direction. The second width is greater than the first width.

## Claims

### Claim 1

A semiconductor structure, comprising:
a circuit cell having transistors, wherein each of the transistors comprises:
nanostructures vertically stacked from each other; and
a gate structure wrapping around the nanostructures and extending in a first direction;
a dielectric gate structure extending in the first direction and adjacent to the circuit cell in a second direction that is perpendicular to the first direction;
a first source/drain feature between adjacent two of the gate structures;
a second source/drain feature between one of the gate structures and the dielectric gate structure;
a first source/drain contact over the first source/drain feature and having a first width in the second direction; and
a second source/drain contact over the second source/drain feature and having a second width in the second direction, wherein the second width is greater than the first width.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein a ratio of the second width to the first width is in a range from about 1.05 to about 1.25.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the first width is in a range from about 6 nm to about 30 nm and the second width is in a range from about 6 nm to about 30 nm.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, further comprising:
gate spacers on sidewalls of the gate structures and the dielectric gate structure.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein:
the first source/drain feature and the second source/drain feature each has a third width in the second direction, and
the third width is greater than the first width and the second width.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the second source/drain contact is in contact with the gate spacer on the sidewall of the dielectric gate structure.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a power conductor overlapping a cell boundary in a top view; and
a via electrically connecting the second source/drain contact to the power conductor.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, further comprising:
contact sidewall layers surrounding the first source/drain contact and the second source/drain contact.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the contact sidewall layers include dielectric material selected from a group consisting of Si3N4, SiON, SiOC, SiOCN, or a combination thereof.

### Claim 10 (depends on 8)

The semiconductor structure of claim 8, wherein the contact sidewall layers have a thickness in a range from about 0.3 nm to about 2 nm.

### Claim 11

A semiconductor structure, comprising:
circuit cells, wherein each of the circuit cells comprises:
nanostructures vertically stacked from each other; and
gate structures wrapping around the nanostructures and extending in a first direction;
dielectric gate structures extending in the first direction and separating the circuit cells from each other in a second direction that is perpendicular to the first direction;
gate spacers on sidewalls of the gate structures and the dielectric gate structure;
first source/drain features, wherein each of the first source/drain features is between adjacent two of the gate structures;
second source/drain features, wherein each of the second source/drain features is between one of the gate structures and one of the dielectric gate structures;
first source/drain contacts over the first source/drain features and extending in the first direction; and
second source/drain contacts over the second source/drain features and extending in the first direction, wherein a width of the second source/drain contacts is greater than a width of the second source/drain contacts.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein each of the second source/drain contacts is closer to the one of the dielectric gate structures than to the one of the gate structures.

### Claim 13 (depends on 11)

The semiconductor structure of claim 11, further comprising:
contact sidewall layers on sidewalls of the first source/drain contacts and sidewalls of the second source/drain contacts.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein the contact sidewall layers on the sidewalls of the second source/drain contact are in contact with the gate spacers on the sidewalls of the dielectric gate structure.

### Claim 15 (depends on 13)

The semiconductor structure of claim 13, wherein the contact sidewall layers on the sidewalls of the second source/drain contact are separated from the gate spacers on the sidewalls of the dielectric gate structure.

### Claim 16 (depends on 11)

The semiconductor structure of claim 11, further comprising:
an inter-layer dielectric layer over the gate structures, the dielectric gate structures, the first source/drain contacts, and the second source/drain contacts, wherein the gate structures are in direct contact with the inter-layer dielectric layer.

### Claim 17 (depends on 11)

The semiconductor structure of claim 11, further comprising:
a power conductor extending in the second direction and electrically connected to the second source/drain contacts.

### Claim 18

A semiconductor structure, comprising:
a circuit cell, wherein the circuit cell comprises:
a first gate structure extending in a first direction and wrapping around first nanostructures vertically stacked from each other; and
a second gate structure extending in the first direction, wrapping around second nanostructures that are vertically stacked from each other, and adjacent to
the first gate structure in a second direction that is perpendicular to the first direction;
a dielectric gate structure extending in the first direction and on a cell boundary of the circuit cell;
a first source/drain feature between the first gate structure and the second gate structure;
a second source/drain feature between the second gate structure and the dielectric gate structure;
a first source/drain contact over the first source/drain feature and having a first width in the second direction; and
a second source/drain contact over the second source/drain feature and having a second width greater than the first width in the second direction.

### Claim 19 (depends on 18)

The semiconductor structure of claim 18, wherein the second source/drain contact extends in the first direction to overlap the cell boundary of the circuit cell in a top view.

### Claim 20 (depends on 18)

The semiconductor structure of claim 18, wherein a distance from the second source/drain contact to the second gate structure is greater than a distance from the second source/drain contact to the dielectric gate structure.