# US 2023/0411368 A1 · Semiconductor device including a circuit for transmitting a signal > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0411368 A1 - Document ID: US20230411368A1 - Status: Published application - Kind: A1 - Application number: 18/461,884 - Filed: 2023-09-06 - Published: 2023-12-21 - Earliest claimed: 2018-06-27 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Toshihiko AKIBA; Kenji SAKATA; Nobuhiro KINOSHITA; Yosuke KATSURA - Web page: https://patentgrep.com/patent/US20230411368A1 ## CPC - H10W 90/00: Package configurations - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 72/00: Interconnections or connectors in packages - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/611: {for connecting multiple chips together} - H10W 72/013: {of die-attach connectors} - H10W 72/072: {of bump connectors} - H10W 72/073: {of die-attach connectors} - H10W 72/07354: {changes in dispositions} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/347: {Dispositions of multiple die-attach connectors} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics} - H10W 72/354: {comprising polymers} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/90: Bond pads, in general - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Reliability of a semiconductor device is improved. The semiconductor device includes a wiring substrate, a semiconductor chip and a capacitor mounted on the upper surface of the wiring substrate, and a lid formed of a metallic plate covering the semiconductor chip and the wire in substrate. The semiconductor chip is bonded to the lid via a conductive adhesive layer, and the capacitor, which is thicker than the thickness of the semiconductor chip, is disposed in the cut off portion provided in the lid, and is exposed from the lid. ## Claims ### Claim 1 A semiconductor device comprising: a wiring substrate having a first main surface and a second main surface opposite the first main surface, the first main surface having a central portion and a peripheral portion surrounding the central portion in plan view; a semiconductor chip having a front surface and a rear surface opposite the front surface, the semiconductor chip being mounted on the central portion of the first main surface of the wiring substrate; a first capacitor mounted on the peripheral portion of the first main surface of the wiring substrate; and a lid disposed over the first main surface of the wiring substrate such that the lid covers the semiconductor chip, the lid having a heat radiation portion and a flange portion surrounding the heat radiating portion, wherein in plan view, the first main surface of the wiring substrate has a rectangular shape comprised of: a first side extending in a first direction; a second side opposite the first side and extending in the first direction; a third side extending in a second direction perpendicular to the first direction; and a fourth side opposite the third side and extending in the second direction, wherein in plan view, the peripheral portion of the first main surface of the wiring substrate has: a first corner portion including a first corner defined by the first side and the third side; a second corner portion including a second corner defined by the third side and the second side; a third corner portion including a third corner defined by the second side and the fourth side; a fourth corner portion including a fourth corner defined by the fourth side and the first side; a first middle portion located between the first corner portion and the second corner portion, in the second direction; a second middle portion located between the second corner portion and the third corner portion, in the first direction; a third middle portion located between the third corner portion and the fourth corner portion, in the second direction; and a fourth middle portion located between the fourth corner portion and the first corner portion, in the first direction, wherein the first capacitor is mounted on the first middle portion of the peripheral portion of the first main surface of the wiring substrate, and wherein the flange portion of the lid is bonded to the wiring substrate via a first adhesive layer at each corner portion of the peripheral portion of the first main surface of the wiring substrate such that the flange portion of the lid is not bonded to the wiring substrate at each middle portion of the peripheral portion of the first main surface of the wiring substrate. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising a second capacitor mounted on the third middle portion of the peripheral portion of the first main surface of the wiring substrate. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the semiconductor chip is mounted on the central portion of the first main surface of the wiring substrate such that the front surface of the semiconductor chip faces the first main surface of the wiring substrate, wherein the heat radiation portion of the lid is bonded to the rear surface of the semiconductor chip via a second adhesive layer, wherein a thickness of the semiconductor chip is thinner than a thickness of each of the first through second capacitors, wherein in cross-sectional view, a mounting height of each of the first through second capacitors from the first main surface of the wiring substrate is higher than a mounting height of the semiconductor chip from the first main surface of the wiring substrate, wherein in plan view, the lid has: a first notched portion concaved from a peripheral edge of the lid toward the heat radiation portion in plan view; and a second notched portion concaved from the peripheral edge of the lid toward the heat radiation portion in plan view, and wherein the lid is disposed over the first main surface of the wiring substrate such that the first capacitor is exposed from the lid at the first notched portion and such that the second capacitor is exposed from the lid at the second notched portion. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, further comprising: a third capacitor mounted on the second middle portion of the peripheral portion of the first main surface of the wiring substrate; and a fourth capacitor mounted on the fourth middle portion of the peripheral portion of the first main surface of the wiring substrate. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the thickness of the semiconductor chip is thinner than a thickness of each of the third through fourth capacitors, wherein in cross-sectional view, a mounting height of each of the third through fourth capacitors from the first main surface of the wiring substrate is higher than the mounting height of the semiconductor chip from the first main surface of the wiring substrate, wherein in plan view, the lid has: a third notched portion concaved from the peripheral edge of the lid toward the heat radiation portion in plan view; and a fourth notched portion concaved from the peripheral edge of the lid toward the heat radiation portion in plan view, and wherein the lid is disposed over the first main surface of the wiring substrate such that the third capacitor is exposed from the lid at the third notched portion and such that the fourth capacitor is exposed from the lid at the fourth notched portion. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein each of the first capacitor and the second capacitor is a DC (Direct Current) cutting capacitor, and wherein each of the third capacitor and the fourth capacitor is a bypass capacitor. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein each of the first adhesive layer and the second adhesive layer is made of a conductive material, and wherein the flange portion of the lid is connected to an electrode of the wiring substrate via the first adhesive layer, a reference potential being to be applied to the electrode. ### Claim 8 (depends on 4) The semiconductor device according to claim 4, wherein the thickness of the semiconductor chip is thinner than a thickness of each of the third through fourth capacitors, wherein in cross-sectional view, a mounting height of each of the third through fourth capacitors from the first main surface of the wiring substrate is higher than the mounting height of the semiconductor chip from the first main surface of the wiring substrate, wherein in plan view, the lid has a first opening portion and a second opening portion, and wherein the lid is disposed over the first main surface of the wiring substrate such that the third capacitor is exposed from the lid at the first opening portion and such that the fourth capacitor is exposed from the lid at the second opening portion. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein each of the first capacitor and the second capacitor is a DC (Direct Current) cutting capacitor, and wherein each of the third capacitor and the fourth capacitor is a bypass capacitor. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein each of the first adhesive layer and the second adhesive layer is made of a conductive material, and wherein the flange portion of the lid is connected to an electrode of the wiring substrate via the first adhesive layer, a reference potential being to be applied to the electrode. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor chip is mounted on the central portion of the first main surface of the wiring substrate such that the front surface of the semiconductor chip faces the first main surface of the wiring substrate, wherein the heat radiation portion of the lid is bonded to the rear surface of the semiconductor chip via a second adhesive layer, wherein a thickness of the semiconductor chip is thinner than a thickness of the first capacitor, wherein in cross-sectional view, a mounting height of the first capacitor from the first main surface of the wiring substrate is higher than a mounting height of the semiconductor chip from the first main surface of the wiring substrate, wherein in plan view, the lid has a first notched portion concaved from a peripheral edge of the lid toward the heat radiation portion in plan view, and wherein the lid is disposed over the first main surface of the wiring substrate such that the first capacitor is exposed from the lid at the first notched portion. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, further comprising: a fifth capacitor mounted on the central portion of the first main surface of the wiring substrate, wherein a thickness of the semiconductor chip is thinner than a thickness of the fifth capacitor, wherein in cross-sectional view, a mounting height of the fifth capacitor from the first main surface of the wiring substrate is higher than a mounting height of the semiconductor chip from the first main surface of the wiring substrate, wherein in plan view, the lid has a first opening portion provided in the heat radiation portion, and wherein the lid is disposed over the first main surface of the wiring substrate such that the fifth capacitor is exposed from the lid at the first opening portion. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the first capacitor is a DC (Direct Current) cutting capacitor, and wherein the fifth capacitor is a bypass capacitor. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the first adhesive layer is made of a conductive material, and wherein the flange portion of the lid is connected to an electrode of the wiring substrate via the first adhesive layer, a reference potential being to be applied to the electrode. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein the first adhesive layer is made of a conductive material, and wherein the flange portion of the lid is connected to an electrode of the wiring substrate via the first adhesive layer, a reference potential being to be applied to the electrode.