# US 2023/0411348 A1 · Chip-first layered packaging architecture

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2023/0411348 A1
- Document ID: US20230411348A1
- Status: Published application
- Kind: A1
- Application number: 17/842,093
- Filed: 2022-06-16
- Published: 2023-12-21
- Earliest claimed: 2022-06-16
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Carlton Hanna; Bernd Waidhas; Thomas Wagner
- Web page: https://patentgrep.com/patent/US20230411348A1

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 90/00: Package configurations
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/095: {of vias therein}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/721: {having structure or size changed during the connecting}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die having first bond-pads on a first surface; an organic dielectric material in contact with the first surface; second bond-pads on a second surface of the organic dielectric material opposite to the first surface; through-dielectric vias (TDVs) in the dielectric material between the first bond-pads and the second bond-pads, wherein the TDVs are in direct contact with the first bond-pads and the second bond-pads; a second IC die embedded in the organic dielectric material and coupled to the first bond-pads by first interconnects; and a package substrate coupled to the second bond-pads by second interconnects.

## Claims

### Claim 1

A microelectronic assembly, comprising:
a first integrated circuit (IC) die having first bond-pads on a first surface;
an organic dielectric material in contact with the first surface;
second bond-pads on a second surface of the organic dielectric material opposite to the first surface;
through-dielectric vias (TDVs) in the organic dielectric material between the first bond-pads and the second bond-pads, wherein the TDVs are in direct contact with the first bond-pads and the second bond-pads;
a second IC die embedded in the organic dielectric material and coupled to the first bond-pads by first interconnects; and
a package substrate coupled to the second bond-pads by second interconnects.

### Claim 2 (depends on 1)

The microelectronic assembly of claim 1, wherein:
the first bond-pads comprise a first subset of bond-pads and a second subset of bond-pads,
the TDVs are in direct contact with the first subset of bond-pads, and
the interconnects between the first IC die and the second IC die are in direct contact with the second subset of bond-pads.

### Claim 3 (depends on 2)

The microelectronic assembly of claim 2, wherein:
the bond-pads in the first subset are spaced apart according to a first pitch,
the bond-pads in the second subset are spaced apart according to a second pitch, and
the first pitch is larger than the second pitch.

### Claim 4 (depends on 2)

The microelectronic assembly of claim 2, wherein: the bond-pads in the first subset are larger than the bond-pads in the second subset.

### Claim 5 (depends on 1)

The microelectronic assembly of claim 1, further comprising an underfill material in the organic dielectric material between the first IC die and the second IC die.

### Claim 6 (depends on 1)

The microelectronic assembly of claim 1, further comprising a third IC die embedded in the organic dielectric material, wherein the second IC die is coupled to the third IC die by third interconnects.

### Claim 7 (depends on 1)

The microelectronic assembly of claim 1 further comprising a polyimide layer, wherein:
a first portion of the organic dielectric material is in contact with the first surface,
the polyimide layer is in contact with the first portion of the organic dielectric material, and
a second portion of the organic dielectric material is in contact with the polyimide layer.

### Claim 8 (depends on 1)

The microelectronic assembly of claim 1 wherein the first surface comprises a polyimide layer in direct contact with the organic dielectric material.

### Claim 9

An interposer, comprising:
an organic dielectric material having a first surface and an opposing second surface;
a first plurality of bond-pads on the first surface;
a second plurality of bond-pads on the second surface;
TDVs between the first plurality of bond-pads and the second plurality of bond-pads; and
one or more IC dies in the organic dielectric material,
wherein:
the first surface is in direct contact with another IC die,
the TDVs are in direct contact with the first plurality of bond-pads and the second plurality of bond-pads.

### Claim 10 (depends on 9)

The interposer of claim 9, wherein the interposer is configured to be coupled to a package substrate through the second plurality of bond-pads.

### Claim 11 (depends on 9)

The interposer of claim 9, wherein:
the first plurality of bond-pads comprises a first subset of bond-pads and a second subset of bond-pads,
the first subset of bond-pads has a first pitch,
the second subset of bond-pads has a second pitch, and
the first pitch is different from the second pitch.

### Claim 12 (depends on 10)

The interposer of claim 10, wherein the second subset of bond-pads is conductively coupled to the one of more IC dies of the interposer.

### Claim 13 (depends on 9)

The interposer of claim 9, wherein at least one IC die in the one or more IC dies is a bridge die configured to laterally couple two other IC dies attached to the first surface of the interposer.

### Claim 14 (depends on 9)

The interposer of claim 9, wherein:
the one or more IC dies include more than one IC die,
the more than one IC dies are arranged in a stack between the first surface and the second surface of the interposer, and
one or more IC dies are in each layer of the stack.

### Claim 15 (depends on 14)

The interposer of claim 14, further comprising TDVs between the first plurality of bond-pads and the IC dies in the stack.

### Claim 16

A method of fabricating an interposer, the method comprising:
providing one or more known good IC dies (KGDs) having first bond-pads;
attaching the KGDs to a carrier;
encapsulating the KGDs with an organic dielectric material;
forming conductive pillars on a first subset of the first bond-pads, wherein the first bond-pads in the first subset have a first pitch;
attaching another KGD to a second subset of the first bond-pads, wherein the first bond-pads in the second subset have a second pitch smaller than the first pitch;
encapsulating the conductive pillars and the another KGD with the organic dielectric material;
planarizing a surface of the organic dielectric material; and
forming second bond-pads on the planarized surface of the organic dielectric material.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming additional TDVs over the another KGD before encapsulating with the organic dielectric material, wherein the additional TDVs are coupled to corresponding conductive pads on the another KGD.

### Claim 18 (depends on 16)

The method of claim 16, further comprising: before forming conductive pillars, depositing a polyimide layer proximate to the first bond-pads.

### Claim 19 (depends on 16)

The method of claim 16, wherein attaching another KGD comprises forming interconnects between the another KGD and the second subset of the bond-pads.

### Claim 20 (depends on 19)

The method of claim 19, further comprising: after forming the interconnects, depositing an underfill material around the interconnects.