# US 2023/0411318 A1 · Semiconductor Device and Method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0411318 A1 - Document ID: US20230411318A1 - Status: Published application - Kind: A1 - Application number: 18/231,032 - Filed: 2023-08-07 - Published: 2023-12-21 - Earliest claimed: 2021-01-14 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Ting-Li Yang; Po-Hao Tsai; Ming-Da Cheng; Yung-Han Chuang; Hsueh-Sheng Wang - Web page: https://patentgrep.com/patent/US20230411318A1 ## CPC - H10W 72/019: {of bond pads} - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/01257: {by reflowing} - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/237: {Multiple bump connectors having different shapes} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/936: {Multiple bond pads having different shapes} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex. ## Claims ### Claim 1 A semiconductor device comprising: a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, wherein a top surface of the first UBM structure is concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, wherein a top surface of the second UBM structure is flat or convex. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first UBM structure has a first width greater than a second width of the second UBM structure. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the first UBM comprises a via portion extending through the first passivation layer, and wherein a centerline of the via portion is misaligned with a centerline of a concave portion of the top surface of the first UBM structure. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the first UBM comprises a via portion extending through the first passivation layer, and wherein a width of the via portion is less than a width of a concave portion of the top surface of the first UBM structure. ### Claim 5 (depends on 1) The semiconductor device of claim 1, further comprising a polymer layer over the first passivation layer, the first UBM structure and the second UBM structure extending through the polymer layer, wherein the UBM structure has a first height over the polymer layer, wherein the second UBM structure has a second height over the polymer layer, and wherein a difference between the first height and the second height is less than 3 μm. ### Claim 6 (depends on 1) The semiconductor device of claim 1, further comprising: a first conductive connector over the first UBM structure, wherein an upper extent of a top surface of the first UBM structure is disposed a first distance over a top surface of the first passivation layer; and a second conductive connector over the second UBM structure, wherein an upper extent of a top surface of the second UBM structure is disposed a second distance over the top surface of the first passivation layer, and wherein a difference between the first distance and the second distance is less than 4 μm. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein an upper extent of the top surface of the first UBM structure is level with an upper extent of the top surface of the second UBM structure. ### Claim 8 A semiconductor device comprising: a first redistribution line and a second redistribution line over a semiconductor substrate; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, wherein a top surface of the first UBM structure is concave, and wherein the first UBM structure has a first width; and a second UBM structure over and electrically coupled to the second redistribution line, wherein a bottom surface of the second UBM structure is level with a bottom surface of the first UBM structure, wherein the second UBM structure has a second width less than the first width, and wherein a top surface of the second UBM structure is less concave than the top surface of the first UBM structure. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the top surface of the second UBM structure is flat. ### Claim 10 (depends on 8) The semiconductor device of claim 8, wherein the top surface of the second UBM structure is convex. ### Claim 11 (depends on 8) The semiconductor device of claim 8, further comprising a first passivation layer over the first redistribution line and the second redistribution line, the first UBM structure and the second UBM structure extending through the first passivation layer, wherein the first UBM structure and the second UBM structure comprise horizontal portions extending along a top surface of the first passivation layer. ### Claim 12 (depends on 8) The semiconductor device of claim 8, further comprising: a first passivation layer over the first redistribution line and the second redistribution line; and a polymer layer over the first passivation layer, wherein the first UBM structure and the second UBM structure extend through the polymer layer and the first passivation layer, and wherein the first UBM structure and the second UBM structure comprise horizontal portions extending along a top surface of the polymer layer. ### Claim 13 (depends on 8) The semiconductor device of claim 8, wherein an upper extent of the top surface of the first UBM structure is level with an upper extent of the top surface of the second UBM structure. ### Claim 14 A semiconductor device comprising: a first conductive feature and a second conductive feature over a semiconductor substrate; a first insulating layer over the first conductive feature and the second conductive feature; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first conductive feature, the first UBM structure extending through the first insulating layer, wherein a top surface of the first UBM structure is a concave surface; and a second UBM structure over and electrically coupled to the second conductive feature, the second UBM structure extending through the first insulating layer, wherein a top surface of the second UBM structure is flat or convex, wherein a first height of the first UBM above the first insulating layer is different than a second height of the second UBM above the first insulating layer. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the first height is in a range between 5 μm to 18 μm. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein a first width of the first UBM is greater than a second width of the second UBM. ### Claim 17 (depends on 14) The semiconductor device of claim 14, wherein a depth of the concave surface of the first UBM is in a range between 0.5 μm to 6 μm. ### Claim 18 (depends on 14) The semiconductor device of claim 14, wherein a difference in the first height and the second height is in a range between 0.01 μm to 3 μm. ### Claim 19 (depends on 14) The semiconductor device of claim 14, wherein the first UBM has a first contact area on the first conductive feature, the second UBM has a second contact area on the second conductive feature, wherein the first contact area is greater than the second contact area. ### Claim 20 (depends on 14) The semiconductor device of claim 14, wherein an upper surface of the second UBM is convex.