# US 2023/0411284 A1 · Semiconductor device with metal spacers and method for fabricating the same

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- Number: US 2023/0411284 A1
- Document ID: US20230411284A1
- Status: Published application
- Kind: A1
- Application number: 18/230,182
- Filed: 2023-08-04
- Published: 2023-12-21
- Earliest claimed: 2019-10-28
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: KUO-HUI SU
- Web page: https://patentgrep.com/patent/US20230411284A1

## CPC

- H10W 20/43: Layouts of interconnections
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0636: {the conductive members being on sidewalls}
- H10W 20/0698: {Local interconnections}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/46: comprising air gaps
- H10W 20/48: Insulating materials thereof
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a semiconductor device including a substrate, an active area in the substrate, a first plug positioned above the active area, second plugs positioned above the active area, metal spacers positioned above the first plug and the plurality of second plugs, and air gaps respectively positioned between the plurality of metal spacers. The active area includes a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
an active area in the substrate, wherein the active area comprises a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view;
a first plug positioned above the active area;
a plurality of second plugs positioned above the active area;
a plurality of metal spacers positioned above the first plug and the plurality of second plugs; and
a plurality of air gaps respectively positioned between the plurality of metal spacers.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first doped region in the active area;
a first insulating film above the substrate and in contact with the first doped region;
a second insulating film above the first insulating film; and
a third insulating film above the second insulating film.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising:
a plurality of second doped regions disposed in the first insulating film; and
a poly line disposed in the first insulating film,
wherein the poly line is disposed between the plurality of second doped regions.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the poly line is disposed over the narrow portion from the top view.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the first plug and the plurality of second plugs are disposed in the second insulating film, and
the first plug is electrically coupled to the poly line through a first contact, and the plurality of second plugs are electrically coupled to the plurality of second doped regions through a plurality of second contacts, respectively.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the plurality of metal spacers are disposed in the third insulating film, and comprise:
a first set of metal spacers;
a second set of metal spacers;
a third set of metal spacers; and
a fourth set of metal spacers,
wherein the second set of metal spacers is positioned between the first set of metal spacers and the third set of metal spacers, and the third set of metal spacers is positioned between the second set of metal spacers and the fourth set of metal spacers.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the first set of metal spacers and the third set of metal spacers are in contact with the plurality of second plugs, respectively.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the second set of metal spacers is in contact with the first plug.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the fourth set of metal spacers is in contact with the second insulating film.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, wherein the first set of metal spacers comprises:
a first metal spacer having a first sidewall and a second sidewall, wherein the first sidewall is perpendicular to a top surface of the second insulating film; and
a second metal spacer attached to the second sidewall of the first metal spacer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein a bottom width of the first set of metal spacers is equal to a top width of one of the plurality of second plugs.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein a bottom width of the first set of metal spacers is greater than a top width of one of the plurality of second plugs.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the first set of metal spacers and the second set of metal spacers are mirror symmetry.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein the first set of metal spacers further comprises:
a first protruding portion extending from a lower portion of the first metal spacer and toward to the second set of metal spacers.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein a width of the first protruding portion is equal to a top width of the one of the plurality of second plugs.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein a width of the first protruding portion is greater than a top width of the one of the plurality of second plugs.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein the second metal spacer is positioned on the first protruding portion.

### Claim 18 (depends on 6)

The semiconductor device of claim 6, wherein the fourth set of metal spacers is a dummy structure.

### Claim 19 (depends on 6)

The semiconductor device of claim 6, wherein the third set of metal spacers comprises:
a third metal spacer positioned having a third sidewall and a fourth sidewall, wherein the third sidewall is perpendicular to a top surface of the second insulating film; and
a fourth metal spacer attached to the fourth sidewall of the third metal spacer.