# US 2023/0411218 A1 · Finfet devices and methods of forming the same

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- Number: US 2023/0411218 A1
- Document ID: US20230411218A1
- Status: Published application
- Kind: A1
- Application number: 18/362,987
- Filed: 2023-08-01
- Published: 2023-12-21
- Earliest claimed: 2018-10-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Hao Wang; Jui-Chien Huang; Kuo-Cheng Ching; Chun-Hsiung Lin; Pei-Hsun Wang
- Web page: https://patentgrep.com/patent/US20230411218A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 14/203: {using transformation of metal, e.g. oxidation or nitridation}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.

## Claims

### Claim 1

A FinFET device, comprising:
a substrate having at least one first fin and an isolation layer covering a lower portion of the at least one first fin, wherein the at least one first fin comprises a first material layer and a second material layer over the first material layer; and
a first gate strip disposed across the at least one first fin and comprising a gate dielectric layer and a gate electrode,
wherein the gate dielectric layer of the first gate strip is in physical contact with the second material layer but separated from the first material layer.

### Claim 2 (depends on 1)

The FinFET device of claim 1, wherein the second material layer has at least one tailing profile toward the isolation layer.

### Claim 3 (depends on 1)

The FinFET device of claim 1, wherein the second material layer covers a sidewall and a top surface of the first material layer.

### Claim 4 (depends on 1)

The FinFET device of claim 1, wherein the at least one first fin above the isolation layer is constituted by the second material layer.

### Claim 5 (depends on 1)

The FinFET device of claim 1, wherein the at least one first fin above the isolation layer is constituted by the second material layer and the first material layer.

### Claim 6 (depends on 1)

The FinFET device of claim 1, wherein the second material layer has a uniform germanium concentration within the at least one first fin above the isolation layer.

### Claim 7 (depends on 1)

The FinFET device of claim 1, wherein the second material layer has a gradient germanium concentration within the at least one first fin above the isolation layer.

### Claim 8 (depends on 1)

The FinFET device of claim 1, wherein the first material layer comprises silicon, and the second material layer comprises silicon germanium.

### Claim 9

A FinFET device, comprising:
a substrate having at least one first fin, wherein the at least one first fin comprises a first material layer and a second material layer over the first material layer, and the second material layer has two tailing portions downwardly toward the substrate; and
a first gate strip disposed across the at least one first fin and comprising a gate dielectric layer and a gate electrode.

### Claim 10 (depends on 9)

The FinFET device of claim 9, further comprising an isolation layer covering a lower portion of the at least one first fin.

### Claim 11 (depends on 10)

The FinFET device of claim 10, wherein the at least one first fin above the isolation layer is constituted by the second material layer.

### Claim 12 (depends on 10)

The FinFET device of claim 10, wherein the at least one first fin above the isolation layer is constituted by the second material layer and the first material layer.

### Claim 13 (depends on 9)

The FinFET device of claim 9, wherein the first material layer comprises a first semiconductor material, and the second material layer comprises a second semiconductor material different from the first semiconductor material.

### Claim 14 (depends on 9)

The FinFET device of claim 9, wherein the first material layer comprises silicon, and the second material layer comprises silicon germanium.

### Claim 15 (depends on 9)

The FinFET device of claim 9, wherein the gate dielectric layer of the first gate strip is in physical contact with the second material layer.

### Claim 16

A method of forming a FinFET device, comprising:
providing a substrate having at least one first fin, the first fin comprising a first material;
forming a second material on a surface of the first fin;
performing an annealing process to drive the second material into the first fin, so the second material layer is tapered downwardly toward the substrate after the annealing process; and
forming a first gate strip across the first fin.

### Claim 17 (depends on 16)

The method of claim 16, wherein an interface between the first material and the second material is uneven.

### Claim 18 (depends on 16)

The method of claim 16, wherein the substrate further has an isolation layer covering a lower portion of the first fin, and the second material of the transforming layer is further driven toward the isolation layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first material of the first fin above the isolation layer is constituted by the second material after the annealing process.

### Claim 20 (depends on 18)

The method of claim 18, wherein the first material of the first fin above the isolation layer is constituted by the second material layer and the first material layer after the annealing process.