# US 2023/0411166 A1 · Method of manufacturing semiconductor structure and semiconductor structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0411166 A1 - Document ID: US20230411166A1 - Status: Published application - Kind: A1 - Application number: 18/150,265 - Filed: 2023-01-05 - Published: 2023-12-21 - Earliest claimed: 2022-06-21 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Yizhi ZENG - Web page: https://patentgrep.com/patent/US20230411166A1 ## CPC - H10P 50/73: {using masks for insulating materials} - H10B 12/033: {the capacitor extending over the transistor} - H10P 14/416: {of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers} - H10P 14/6329: {using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition} - H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD} - H10P 14/69215: {the material being a silicon oxide, e.g. SiO2} - H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H} - H10P 50/71: {using masks for conductive or resistive materials} - H10P 76/408: {characterised by their sizes, orientations, dispositions, behaviours or shapes} - H10P 76/4085: {characterised by the processes involved to create the masks} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a base; forming a first dielectric layer having grooves, where the grooves include a first groove and a second groove whose inner diameters have a first difference; forming an initial filling layer in the first groove and the second groove, where the first groove forms a third groove, the second groove forms a fourth groove, and an inner diameter of the third groove and that of the fourth groove have a second difference less than the first difference; processing the initial filling layer to form a filling layer; and forming a plurality of etching openings whose inner diameters have a preset difference on a surface of the base. ## Claims ### Claim 1 A method of manufacturing a semiconductor structure, comprising: providing a base; forming a first dielectric layer on the base, wherein the first dielectric layer is provided with grooves arranged in an array, the grooves comprise a first groove and a second groove, and an inner diameter of the first groove and an inner diameter of the second groove have a first difference; forming an initial filling layer, wherein the initial filling layer covers a sidewall and a bottom wall of the first groove and covers a sidewall and a bottom wall of the second groove, the initial filling layer in the first groove forms a third groove, the initial filling layer in the second groove forms a fourth groove, an inner diameter of the third groove and an inner diameter of the fourth groove have a second difference, and the second difference is less than the first difference; processing the initial filling layer to form a filling layer; and etching at least one of the filling layer or the first dielectric layer, to form a plurality of etching openings whose inner diameters have a preset difference on a surface of the base. ### Claim 2 (depends on 1) The method of manufacturing a semiconductor structure according to claim 1, wherein the groove has a target size, the inner diameter of the first groove is less than the target size, and the inner diameter of the second groove is greater than the target size; the target size is any value in a range of 30 nm to 60 nm; and the inner diameter of the first groove and the inner diameter of the second groove have a maximum difference of 6 nm. ### Claim 3 (depends on 1) The method of manufacturing a semiconductor structure according to claim 1, wherein the processing the initial filling layer to form a filling layer comprises: performing ion implantation on the initial filling layer; and performing rapid thermal processing on the initial filling layer after the ion implantation, to form the filling layer. ### Claim 4 (depends on 3) The method of manufacturing a semiconductor structure according to claim 3, wherein the performing ion implantation on the initial filling layer comprises: performing ion implantation on the initial filling layer by using a group III or group V element. ### Claim 5 (depends on 4) The method of manufacturing a semiconductor structure according to claim 4, wherein an ion implantation dose is between 1014/cm2 and 1015/cm2, and ion implantation energy is between 10 KeV and 40 KeV. ### Claim 6 (depends on 1) The method of manufacturing a semiconductor structure according to claim 1, wherein the forming an initial filling layer comprises: forming the initial filling layer in the first groove and the second groove by using a chemical vapor deposition process or a physical vapor deposition process. ### Claim 7 (depends on 6) The method of manufacturing a semiconductor structure according to claim 6, wherein a thickness of the initial filling layer is from 5 nm to 8 nm. ### Claim 8 (depends on 1) The method of manufacturing a semiconductor structure according to claim 1, wherein a material of the first dielectric layer comprises one of silicon oxynitride, silicon nitride, silicon oxide, silicon carbide, and a spin-coated hard mask layer. ### Claim 9 (depends on 1) The method of manufacturing a semiconductor structure according to claim 1, wherein the first dielectric layer comprises undoped polysilicon. ### Claim 10 (depends on 1) The method of manufacturing a semiconductor structure according to claim 1, wherein the providing a base comprises: providing a substrate; and forming a support structure on the substrate, wherein the support structure comprises: an isolation layer, a first sacrificial layer, at least one support layer, a second sacrificial layer, and an etching layer that are formed and sequentially stacked on the substrate, and each support layer comprises a first support layer and a spin-coated hard mask layer that are alternately arranged. ### Claim 11 (depends on 10) The method of manufacturing a semiconductor structure according to claim 10, wherein the forming a first dielectric layer on the base, wherein the first dielectric layer is provided with grooves arranged in an array comprises: forming the first dielectric layer on the etching layer; forming a first mask layer on the first dielectric layer; providing a first mask pattern, and removing part of the first mask layer based on the first mask pattern, to form a plurality of initial grooves on the first mask layer; and removing part of the first dielectric layer by using a remaining part of the first mask layer as a mask based on the initial grooves, to form the grooves on the first dielectric layer. ### Claim 12 (depends on 11) The method of manufacturing a semiconductor structure according to claim 11, further comprising: removing part of the etching layer based on the etching openings, to form a plurality of first through holes arranged at intervals along a first direction in the etching layer. ### Claim 13 (depends on 12) The method of manufacturing a semiconductor structure according to claim 12, further comprising: removing part of the second sacrificial layer based on the first through holes, to form a plurality of second through holes arranged at intervals along the first direction in the second sacrificial layer. ### Claim 14 (depends on 13) The method of manufacturing a semiconductor structure according to claim 13, further comprising: forming, based on the second through holes, a plurality of contact holes arranged at intervals along the first direction in the support structure. ### Claim 15 (depends on 1) A semiconductor structure, manufactured by the method of manufacturing a semiconductor structure according to claim 1.