# US 2023/0410885 A1 · Apparatuses and methods for controlling sense amplifier operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0410885 A1 - Document ID: US20230410885A1 - Status: Published application - Kind: A1 - Application number: 17/841,517 - Filed: 2022-06-15 - Published: 2023-12-21 - Earliest claimed: 2022-06-15 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Christopher G. Wieduwilt; John P. Behrend - Web page: https://patentgrep.com/patent/US20230410885A1 ## CPC - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs} - G11C 7/065: {Differential amplifiers of latching type} - G11C 7/08: Control thereof - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Apparatuses and methods for controlling sense amplifier operation are described. An example method includes providing a control signal having a first high logic level voltage to activate isolation switches of a sense amplifier. The control signal transitions from the first high logic level voltage to an inactive voltage to deactivate the isolation switches of the sense amplifier before accessing a memory cell. The control signal is provided having the first high logic level voltage to activate the isolation switches of the sense amplifier after accessing the memory cell. The control signal is increased from the first high logic level voltage to a second high logic level voltage. ## Claims ### Claim 1 An apparatus, comprising: first and second sense lines, each sense line coupled to a respective set of memory cells; a sense amplifier including first and second sense nodes, and further including a first isolation switch and a second isolation switch, the first isolation switch coupled to the first sense node and the first sense line and configured to provide a conductive path between the first sense node and the first sense line when activated, the second isolation switch coupled to the second sense node and the second sense line and configured to provide a conductive path between the second sense node and the second sense line when activated; and a control signal driver circuit configured to receive an input control signal and provide an output control signal to the first and second isolation switches responsive to the input control signal, the control signal driver circuit further configured to provide the output control signal having a first high logic level voltage for a first portion of a sense amplifier operation and provide the active output control signal having a second high logic level voltage for a second portion of the sense amplifier operation when the output control signal is active, the second high logic level voltage greater than the first high logic level voltage. ### Claim 2 (depends on 1) The apparatus of claim 1 wherein the control signal driver comprises: a control logic circuit configured to receive the input control signal and an enable signal, the control logic circuit further configured to provide an intermediate control signal responsive to the input control signal when enabled by an active enable signal; a plurality of inverter circuits coupled in series, a first inverter circuit of the plurality of inverter circuits configured to receive the intermediate control signal and a last inverter circuit of the plurality of inverter circuits configured to provide the output control signal; and a voltage control circuit coupled to at least one of the plurality of inverter circuits and configured to provide a high logic level voltage, the voltage control circuit further configured to provide the high logic level voltage at the first high logic level voltage for the first portion of the sense amplifier operation and to provide the high logic level voltage at the second high logic level voltage for the second portion of the sense amplifier operation. ### Claim 3 (depends on 2) The apparatus of claim 2 wherein the voltage control circuit comprises: a node at which the high logic level voltage is provided; a first voltage switch coupled to the node and configured to provide the first high logic level voltage to the node when activated; and a second voltage switch coupled to the node and configured to provide the second high logic level voltage to the node when activated. ### Claim 4 (depends on 3) The apparatus of claim 3 wherein the first voltage switch is configured to be activated and the second voltage switch is configured to be deactivated during the first portion of the sense amplifier operation and wherein the first voltage switch is configured to be deactivated and the second voltage switch is configured to be activated during the second portion of the sense amplifier operation. ### Claim 5 (depends on 2) The apparatus of claim 2 wherein the voltage control circuit is coupled to at least the last inverter circuit of the plurality of inverter circuits. ### Claim 6 (depends on 1) The apparatus of claim 1, further comprising a precharge circuit coupled to the sense amplifier and configured to precharge voltage nodes of the sense amplifier to a precharge voltage. ### Claim 7 (depends on 1) The apparatus of claim 1 wherein the sense amplifier is a threshold voltage compensated sense amplifier. ### Claim 8 An apparatus, comprising: a first sense line and a second sense line; a sense amplifier including a first isolation switch coupled to a first sense node and the first sense line, and including a second isolation switch coupled to a second sense node and the second sense line; and a control signal driver configured to provide a control signal to the first and second isolation switches of the sense amplifier, the control signal driver configured to provide the control signal to activate the first and second isolation switches having a first high logic level voltage or a second high logic level voltage, the second high logic level voltage greater than the first high logic level voltage. ### Claim 9 (depends on 8) The apparatus of claim 8 wherein the control signal driver is further configured to transition the control signal from the first high logic level voltage to an inactive voltage to deactivate the first and second isolation switches. ### Claim 10 (depends on 8) The apparatus of claim 8 wherein the control signal driver is further configured to transition the control signal from an inactive voltage to the first high logic level voltage to activate the first and second isolation switches, and to increase the control signal from the first high logic level voltage to the second high logic level voltage thereafter. ### Claim 11 (depends on 10) The apparatus of claim 10 wherein the sense amplifier is configured to be activated after the first and second isolation switches and before the control signal increases from the first high logic level voltage to the second high logic level voltage. ### Claim 12 (depends on 10) The apparatus of claim 10 wherein the sense amplifier is further configured to be precharged and wherein the control signal driver is further configured to decrease a high logic level voltage for the control signal from the second high logic level voltage to the first high logic level voltage when the sense amplifier is precharged. ### Claim 13 (depends on 10) The apparatus of claim 10 wherein the sense amplifier is configured to be threshold voltage compensated and wherein the control signal driver is further configured to decrease a high logic level voltage for the control signal from the second high logic level voltage to the first high logic level voltage during threshold voltage compensation of the sense amplifier. ### Claim 14 A method, comprising: deactivating isolation switches of a sense amplifier by transitioning a control signal from a first high logic level voltage to an inactive voltage before a sense phase of a sense amplifier operation; activating the isolation switches of the sense amplifier by transitioning the control signal from the inactive voltage to the first high logic level voltage before an amplification phase of the sense amplifier operation; and increasing the control signal to a second high logic level voltage during the amplification phase. ### Claim 15 (depends on 14) The method of claim 14, further comprising compensating a threshold voltage difference between pull-down circuits of the sense amplifier during a threshold voltage compensation phase after the isolation switches are deactivated. ### Claim 16 (depends on 14) The method of claim 14, further comprising precharging the sense amplifier during a precharge operation after the amplification phase. ### Claim 17 (depends on 14) The method of claim 14 wherein the amplification phase comprises activating the sense amplifier, and the control signal is increases to the second high logic level voltage after the sense amplifier is activated. ### Claim 18 (depends on 14) The method of claim 14 wherein transitioning the control signal from the inactive voltage to the first high logic level voltage comprises driving the control signal with the first high logic level voltage, and wherein increasing the control signal to the second high logic level voltage comprises driving the control signal with the second high logic level voltage instead of the first high logic level voltage. ### Claim 19 A method, comprising: providing a control signal having a first high logic level voltage to activate isolation switches of a sense amplifier; transitioning the control signal from the first high logic level voltage to an inactive voltage to deactivate the isolation switches of the sense amplifier before accessing a memory cell; providing the control signal having the first high logic level voltage to activate the isolation switches of the sense amplifier after accessing the memory cell; and increasing the control signal from the first high logic level voltage to a second high logic level voltage. ### Claim 20 (depends on 19) The method of claim 19, further comprising activating the sense amplifier after accessing the memory cell and before increasing the control signal from the first high logic level voltage to the second high logic level voltage. ### Claim 21 (depends on 19) The method of claim 19, further comprising precharging the sense amplifier, and decreasing the control signal from the second high logic level voltage to the first high logic level voltage when precharging the sense amplifier. ### Claim 22 (depends on 19) The method of claim 19, further comprising compensating for a threshold voltage difference of the sense amplifier. ### Claim 23 (depends on 19) The method of claim 19 wherein providing a control signal having a first high logic level voltage comprises providing the first high logic level voltage to a node that provides a voltage to drive the high logic level control signal, and wherein increasing the control signal from the first high logic level voltage to a second high logic level voltage comprises providing the second high logic level voltage to the node instead of providing the first high logic level voltage.