# US 2023/0410243 A1 · Multicore master/slave communications > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0410243 A1 - Document ID: US20230410243A1 - Status: Published application - Kind: A1 - Application number: 18/127,579 - Filed: 2023-03-28 - Published: 2023-12-21 - Earliest claimed: 2022-03-30 - Assignees: Imagination Technologies Limited - Applicants: Imagination Technologies Limited - Inventors: Michael John Livesley; Ian King - Web page: https://patentgrep.com/patent/US20230410243A1 ## CPC - G06F 9/5066: {Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451)} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/505: {considering the load} - G06F 9/544: {Buffers; Shared memory; Pipes} - G06F 15/80: comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract A master unit in a core of a plurality of cores in a graphics processing unit receives a set of image rendering tasks, assigns a first subset of the image rendering tasks to a first core of the plurality of cores and assigns a second subset of the image rendering tasks to a second core of the plurality of cores. The master unit transmits the first subset of image rendering tasks to a slave unit of the first core and transmits the second subset of image rendering tasks to a slave unit of the second core. The master unit stores a credit number for each of the first and second cores and adjusts the credit number of the first and second cores by a first amount for each task in the first and second subset of the image rendering tasks. The slave units transmit credit notifications when tasks have been processed and the master unit adjusts the credit numbers when it receives the notifications. ## Claims ### Claim 1 A graphics processing unit comprising a plurality of cores, wherein each core of the plurality of cores comprises a slave unit configured to manage the execution of image rendering tasks within the core, and wherein at least one of the plurality of cores further comprises a master unit configured to: receive a set of image rendering tasks; assign a first subset of the image rendering tasks to a first core of the plurality of cores; assign a second subset of the image rendering tasks to a second core of the plurality of cores; transmit the first subset of the image rendering tasks to the slave unit of the first core; and transmit the second subset of the image rendering tasks to the slave unit of the second core; wherein: the slave unit of the first core is configured to transmit to the master unit a first credit notification when a task in the first subset of the image rendering tasks has been processed, the slave unit of the second core is configured to transmit to the master unit a second credit notification when a task in the second subset of the image rendering tasks has been processed; and the master unit is configured to: store a credit number for each of the first and second cores, adjust the credit number of the first core by a first amount for each task in the first subset of the image rendering tasks when the master unit assigns the first subset of the image rendering tasks to the first core, adjust the credit number of the second core by the first amount for each task in the second subset of the image rendering tasks when the master unit assigns the second subset of the image rendering tasks to the second core, adjust the credit number of the first core by a second amount when the master unit receives the first credit notification, and adjust the credit number of the second core by the second amount when the master unit receives the second credit notification, wherein one of the first and second amounts is positive, and the other is negative. ### Claim 2 (depends on 1) The graphics processing unit of claim 1, wherein the master unit is configured to: assign a subsequent image rendering task to the slave unit of the core with the least work currently assigned to it, based on the credit number of each of the cores; adjust the credit number of the core to which the subsequent image rendering task has been assigned by the first amount; and transmit the subsequent image rendering task to the slave unit of the core to which it has been assigned. ### Claim 3 (depends on 2) The graphics processing unit of claim 2, wherein: the first core comprises a first number of available processing units (PUs), configured to perform rendering operations, and the second core comprises a second number of available PUs; and the master unit assigns image rendering tasks to the first and second cores in direct relation to the first and second numbers of available PUs. ### Claim 4 (depends on 1) The graphics processing unit of claim 1, wherein: the first subset of the image rendering tasks comprises a first task, wherein the first task is a task on which a dependent task depends; the master unit is configured to include, in the first subset of the image rendering tasks and following the first task, a task completion update command; the slave unit of the first core is configured to send a first task completion update to the master unit when the first core processes the task completion update command; the master unit is configured to assign and transmit a dependent task of the first task to one of the slave units of the first and second cores only after the master unit has received the first task completion update; and the dependent task of the first task is a task that depends on the results of the first task. ### Claim 5 (depends on 1) The graphics processing unit of claim 1, wherein each core in the plurality of cores comprises a second slave unit configured to manage the execution of a second type of image rendering task by the core, and wherein one of the cores comprises a second master unit configured to: receive a second set of image rendering tasks of the second type; assign a first subset of the second set of image rendering tasks to a first one of the plurality of cores; assign a second subset of the second set of image rendering tasks to a second, different one of the plurality of cores; transmit the first subset of the second set of image rendering tasks to the second slave unit of the first one of the plurality of cores; and transmit the second subset of the second set of image rendering tasks to the second slave unit of the second one of the plurality of cores. ### Claim 6 (depends on 1) The graphics processing unit of claim 1, wherein: the master unit is configured to output first and second register write commands; the first register write command is addressed to the first core and comprises an indication of the first subset of the image rendering tasks, and the second register write command is addressed to the second core and comprises an indication of the second subset of the image rendering tasks; and the plurality of cores are connected by a register bus configured to communicate register write commands between the cores. ### Claim 7 (depends on 6) The graphics processing unit of claim 6, wherein at least the core comprising the master unit further comprises an arbiter unit in communication with the master unit and the slave unit of the core, wherein the arbiter unit is configured to: receive the register write commands from the master unit; and for each register write command: if the register write command is addressed to the core comprising the master unit, pass the register write command to the slave unit of the core comprising the master unit; and if the register write command is not addressed to the core comprising the master unit, forward the register write command for transmission over the register bus. ### Claim 8 (depends on 6) The graphics processing unit of claim 6, wherein the plurality of cores each comprise an interface unit in communication with the register bus, wherein the interface unit of the core comprising the master unit is configured to: receive the first and second register write commands; and transmit, over the register bus, the first register write command to the first core and the second register write command to the second core; wherein the interface unit of the first core is configured to: receive, via the register bus, the first register write command, and forward the first register write command to the slave unit of the first core; and wherein the interface unit of the second core is configured to: receive, via the register bus, the second register write command, and forward the second register write command to the slave unit of the second core. ### Claim 9 (depends on 8) The graphics processing unit of claim 8, wherein the interface unit of the first core is configured to: determine whether the first register write command is addressed to a first reserved register address; and if the first register write command is addressed to the first reserved register address, forward the first register write command to the slave unit of the first core, and wherein the interface unit of the second core is configured to: determine whether the second register write command is addressed to a second reserved register address; and if the second register write command is addressed to the second reserved register address, forward the second register write command to the slave unit of the second core. ### Claim 10 A method of transmitting image rendering tasks in a graphics processing unit comprising a plurality of cores, the method comprising: receiving, by a master unit in a core of the plurality of cores, a set of image rendering tasks; assigning, by the master unit, a first subset of the image rendering tasks to a first core of the plurality of cores; assigning, by the master unit, a second subset of the image rendering tasks to a second core of the plurality of cores; transmitting, by the master unit, the first subset of image rendering tasks to a slave unit of the first core; transmitting, by the master unit, the second subset of image rendering tasks to a slave unit of the second core; storing, by the master unit, a credit number for each of the first and second cores; adjusting, by the master unit, the credit number of the first core by a first amount for each task in the first subset of the image rendering tasks; and adjusting, by the master unit, the credit number of the second core by the first amount for each task in the second subset of image rendering tasks; transmitting, by the slave unit of the first core to the master unit, a first credit notification when a task in the first subset of image rendering tasks has been processed; transmitting, by the slave unit of the second core to the master unit, a second credit notification when a task in the second subset of image rendering tasks has been processed; adjusting, by the master unit, the credit number of the first core by a second amount when the master unit receives the first credit notification; and adjusting, by the master unit, the credit number of the second core by the second amount when the master unit receives the second credit notification, wherein one of the first and second amounts is positive, and the other is negative. ### Claim 11 (depends on 10) The method of claim 10, further comprising: assigning, by the master unit, a subsequent image rendering task to the slave unit of the core with the least work currently assigned to it, based on the credit number of each of the cores; adjusting, by the master unit, the credit number of the core to which the subsequent image rendering task has been assigned by the first amount; and transmitting, by the master unit, the subsequent image rendering task to the slave unit of the core to which it has been assigned. ### Claim 12 (depends on 10) The method of claim 10, further comprising: assigning image rendering tasks to the first and second cores in direct relation to a first number of available processing units (PUs), and to a second number of available PUs, wherein the first number of available PUs is the number of available PUs in the first core and the second number of available PUs is the number of available PUs in the second core. ### Claim 13 (depends on 10) The method of claim 10, wherein the method comprises: including, by the master unit, after a first task in the first subset of the image rendering tasks, a task completion update command; processing, by the first core, the first task; processing, by the first core, the task completion update command; and transmitting, by the slave unit of the first core, a task completion update to the master unit; assigning, by the master unit, a dependent task of the first task to one of the slave units of the first and second cores; and transmitting, by the master unit, the dependent task to the core to which it has been assigned. ### Claim 14 (depends on 13) The method of claim 13, further comprising: including, by the master unit, after the first task in the first subset of the image rendering tasks and optionally before the task completion update command, a memory flush command; processing, by the first core, the memory flush command; and writing, by the slave unit of the first core, all output data stored in the first core to a shared memory. ### Claim 15 (depends on 10) The method of claim 10, further comprising: receiving, by a second master unit in any one of the plurality of cores, a second set of image rendering tasks of a second type; assigning, by the second master unit, a first subset of the second set of image rendering tasks to the first core; assigning, by the second master unit, a second subset of the second set of image rendering tasks to the second core; transmitting, by the second master unit, the first subset of the second set of image rendering tasks to a second slave unit of the first core; and transmitting, by the second master unit, the second subset of the second set of image rendering tasks to a second slave unit of the second core. ### Claim 16 (depends on 10) The method of claim 10, wherein: the transmitting of the first and second subsets comprises outputting, by the master unit, first and second register write commands; the first register write command is addressed to the first core and comprises an indication of the first subset of the image rendering tasks, and the second register write command is addressed to the second core and comprises an indication of the second subset of the image rendering tasks; and the plurality of cores are connected by a register bus for communicating the register write commands between the cores. ### Claim 17 (depends on 1) A method of manufacturing a graphics processing unit as set forth in claim 1, the method comprising inputting to an integrated circuit manufacturing system an integrated circuit definition dataset that, when processed in said integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture said graphics processing unit. ### Claim 18 (depends on 10) A non-transitory computer readable storage medium having stored thereon computer readable code configured to cause the method as set forth in claim 10 to be performed when the code is run. ### Claim 19 (depends on 1) A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a graphics processing unit as set forth in claim 1 that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the graphics processing unit. ### Claim 20 (depends on 1) An integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a graphics processing unit as set forth in claim 1; a layout processing system configured to process the computer readable dataset description so as to generate a circuit layout description of an integrated circuit embodying the graphics processing unit; and an integrated circuit generation system configured to manufacture the graphics processing unit according to the circuit layout description.