Data flow management
AssigneeXConn Technologies Holdings, Inc.
InventorsChristopher Helps, Yan Fan
Life of this patent
Estimating the term…
Abstract
A switch is described. The switch includes a plurality of ports, a plurality of port logic modules, a memory, and a switch fabric. Transactions ingress and egress the switch via the ports. The port logic modules are coupled with the ports. Each port logic module has core clock domain logic for a core clock domain specific to a corresponding port. The memory includes banks. The memory and the switch fabric have a system clock domain. The core clock domain for each of the port logic modules is different from the system clock domain.
Claims19
A switch, comprising:
- a plurality of ports through which transactions ingress and egress the switch;
- a plurality of port logic modules coupled with the plurality of ports, each port logic module having core clock domain logic for a core clock domain specific to a corresponding port of the plurality of ports;
- a memory including a plurality of banks;
- and
- a switch fabric, wherein the memory and the switch fabric have a system clock domain, the core clock domain for each of the plurality of port logic modules being different from the system clock domain.
A Compute Express Link Internet Protocol (CXL IP) switch, comprising:
- a plurality of ports through which transactions ingress and egress the CXL IP switch;
- a plurality of port logic modules coupled with the plurality of ports, each port logic module having core clock domain logic for a core clock domain specific to a corresponding port of the plurality of ports, each port logic module including a clock domain crossing (CDC) first-in-first-out (FIFO) buffer, the CDC FIFO buffer being configured for managing a transition between the core clock domain and a system clock domain, each port control logic module being configured to combine a first number of port streams from the corresponding port to a second number of system streams and to separate the second number of system streams into the first number of port streams, each port control logic module controlling flow through the port for a host via credit granting, the port control logic module configured to decrement a pending credit count for the host based on a write request for a pending credit buffer and increment the pending credit count for a read request for the pending credit buffer, each port logic module further including routing logic, the routing logic configured to allow a response transaction to bypass a request transaction and to prevent the request transaction from bypassing the response transaction;
- a memory including a plurality of banks;
- and
- a switch fabric, wherein the memory and the switch fabric have the system clock domain, the core clock domain for each of the plurality of port logic modules being different from the system clock domain.
A method, comprising:
- receiving a transaction in a port of a plurality of ports of a switch, the switch also including a plurality of port logic modules and a core portion, the core portion including a switch fabric and a memory, the plurality of port logic modules being coupled with the plurality of ports, a port logic module of the plurality of port logic modules being coupled with the port, the core portion of the switch having a system clock domain;
- and
- controlling, using the port logic module, routing of the transaction through the core portion, the port logic module having core clock domain logic for a core clock domain specific to the port and different from the system clock domain.
Dependencies are inferred from the claim text.