Technique for constraining access to memory using capabilities

An apparatus comprising:

• processing circuitry to perform operations during which access requests to memory are generated, wherein the processing circuitry is arranged to generate memory addresses for the access requests using capabilities that identify constraining information;
• capability checking circuitry to perform a capability check operation to determine whether a given access request whose memory address is generated using a given capability is permitted based on the constraining information identified by that given capability;
• and
• memory access checking circuitry to further constrain access to the memory by the given access request in dependence on a level of trust associated with the given access request;
• wherein:
• the given capability has a capability level of trust associated therewith, and the level of trust associated with the given access request is dependent on both a current mode level of trust associated with a current mode of operation of the processing circuitry, and the capability level of trust of the given capability.

A method of constraining access to memory, comprising:

• employing processing circuitry to perform operations during which access requests to memory are generated, wherein the processing circuitry generates memory addresses for the access requests using capabilities that identify constraining information;
• performing a capability check operation to determine whether a given access request whose memory address is generated using a given capability is permitted based on the constraining information identified by that given capability;
• and
• further constraining access to the memory by the given access request in dependence on a level of trust associated with the given access request, wherein the given capability has a capability level of trust associated therewith, and the level of trust associated with the given access request is dependent on both a current mode level of trust associated with a current mode of operation of the processing circuitry, and the capability level of trust of the given capability.

A computer program for controlling a host data processing apparatus to provide an instruction execution environment, comprising:

• processing program logic to perform operations during which access requests to memory are generated, wherein the processing program logic is arranged to generate memory addresses for the access requests using capabilities that identify constraining information;
• capability checking program logic to perform a capability check operation to determine whether a given access request whose memory address is generated using a given capability is permitted based on the constraining information identified by that given capability;
• and
• memory access checking program logic to further constrain access to the memory by the given access request in dependence on a level of trust associated with the given access request;
• wherein:
• the given capability has a capability level of trust associated therewith, and the level of trust associated with the given access request is dependent on both a current mode level of trust associated with a current mode of operation of the processing program logic, and the capability level of trust of the given capability.