# US 2023/0409491 A1 · Memory device with cryptographic kill switch

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- Number: US 2023/0409491 A1
- Document ID: US20230409491A1
- Status: Published application
- Kind: A1
- Application number: 18/448,862
- Filed: 2023-08-11
- Published: 2023-12-21
- Earliest claimed: 2019-06-18
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Gil Golov
- Web page: https://patentgrep.com/patent/US20230409491A1

## CPC

- G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)}
- H04L 9/0897: {involving additional devices, e.g. trusted platform module [TPM], smartcard or USB}
- G06F 12/1433: {for a module or a part of a module}
- G06F 12/1466: {Key-lock mechanism}
- H04L 9/0825: {using asymmetric-key encryption or public key infrastructure [PKI], e.g. key signature or public key certificates}
- H04L 9/14: using a plurality of keys or algorithms
- H04L 9/30: Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
- G06F 2212/1052: Security improvement
- G06F 2212/173: Vehicle or other transportation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

The disclosed embodiments describe devices and methods for preventing unauthorized access to memory devices. The disclosed embodiments utilize a one-time programmable (OTP) memory added to both a memory device and a processing device. The OTP memory stores encryption keys and the encryption and decryption of messages between the two devices are used as a heartbeat to determine that the memory device has not been separated from the processing device and, in some instances, connected to a malicious processing device.

## Claims

### Claim 1

A method comprising:
disabling, by a memory device, an interface in response to detecting that a challenge failed;
decrypting, by the memory device, a second response;
scrubbing, by the memory device, a memory bank; and
lowering, by the memory device, a signal on the interface.

### Claim 2 (depends on 1)

The method of claim 1, the interface comprising a command/address interface.

### Claim 3 (depends on 1)

The method of claim 1, the decrypting the second response comprising decrypting the second response using a shared private key.

### Claim 4 (depends on 1)

The method of claim 1, wherein detecting that a challenge failed comprises executing a background process to detect an authentication failure.

### Claim 5 (depends on 4)

The method of claim 4, wherein detecting the authentication failure comprises detecting an absence of a processing device connected to the memory device.

### Claim 6 (depends on 1)

The method of claim 1, wherein scrubbing the memory bank comprises issuing a RESET command to the memory device.

### Claim 7 (depends on 1)

The method of claim 1, wherein lowering the signal comprises driving lines of the interface to logical one.

### Claim 8

A device comprising:
an interface;
a memory array having one or more memory banks;
control logic communicatively coupled to the memory array, the control logic configured to:
disable an interface in response to detecting that a challenge failed;
decrypt a second response;
scrub a memory bank; and
lower a signal on the interface.

### Claim 9 (depends on 8)

The device of claim 8, the interface comprising a command/address interface.

### Claim 10 (depends on 8)

The device of claim 8 the decrypting the second response comprising decrypting the second response using a shared private key.

### Claim 11 (depends on 8)

The device of claim 8, wherein detecting that a challenge failed comprises executing a background process to detect an authentication failure.

### Claim 12 (depends on 11)

The device of claim 11, wherein detecting the authentication failure comprises detecting an absence of a processing device connected to the device.

### Claim 13 (depends on 8)

The device of claim 8, wherein scrubbing the memory bank comprises issuing a RESET command to the device.

### Claim 14 (depends on 8)

The device of claim 8, wherein lowering the signal comprises driving lines of the interface to logical one.

### Claim 15

A non-transitory computer readable storage medium for tangibly storing computer program instructions capable of being executed by a processor, the computer program instructions defining steps of:
disabling an interface in response to detecting that a challenge failed;
decrypting a second response;
scrubbing a memory bank; and
lowering a signal on the interface.

### Claim 16 (depends on 15)

The non-transitory computer readable storage medium of claim 15, the interface comprising a command/address interface.

### Claim 17 (depends on 15)

The non-transitory computer readable storage medium of claim 15, the decrypting the second response comprising decrypting the second response using a shared private key.

### Claim 18 (depends on 15)

The non-transitory computer readable storage medium of claim 15, wherein detecting that a challenge failed comprises executing a background process to detect an authentication failure.

### Claim 19 (depends on 18)

The non-transitory computer readable storage medium of claim 18, wherein detecting the authentication failure comprises detecting an absence of a processing device connected to the processor.

### Claim 20 (depends on 15)

The non-transitory computer readable storage medium of claim 15, wherein scrubbing the memory bank comprises issuing a RESET command to the memory bank.