Apparatus and Method for Selecting Dynamic Latency for Level 2 Cache
AssigneeCondor Computing Corporation
InventorsThang Tran, Shashank Nemawarkar, Raul Garibay
Life of this patent
Estimating the term…
Abstract
A processor includes a time counter and issuing instruction and executing instruction at a future time which is based on the time counter. The execution times are based on fixed latency times of instructions with exception of the load instruction which is based on the data cache hit latency time. A data cache miss causes the load instruction to fetch data from the level 2 cache wherein a time tracker unit adjusts the level 2 cache latency time based on a counter.
Claims20
A processor comprising:
- a time counter storing a time count representing a current time of the processor, wherein the time count is incremented with each clock cycle of a clock circuit;
- a load store unit coupled to a data cache to fetch data for a first load instruction and wherein the data for the first load instruction is not in the data cache;
- the load store unit coupled to a level 2 cache to fetch the data for the first load instruction, wherein the level 2 cache is expected to return data with a predicted latency time, and wherein the predicted latency time corresponds to the time count;
- and
- a time tracker unit coupled to the load store unit to track an actual level 2 cache response time and to adjust the predicted latency time for subsequent accesses to the level 2 cache.
A method implemented in a processor to select a different level 2 cache latency time than a current level 2 cache latency time based on a time tracker, wherein data from the level 2 cache is returned to a load store unit at a future time, wherein the future time is defined by the level 2 cache latency time and a time count in which the time count is incremented with each clock cycle of a clock circuit.
A processor comprising:
- a time counter adapted to store a time count, said time count representing a current time of said processor, said time count being incremented as a function of each clock cycle of a clock circuit;
- a load store unit coupled to a data cache, said data cache being adapted to fetch data for a first load instruction, said data for a first load instruction being further characterized as absent from said data cache;
- said load store unit further coupled to a level 2 cache, said level 2 cache being adapted to fetch said data for a first load instruction, said level 2 cache being adapted to return data in accordance with a predicted latency time, said predicted latency time corresponds to said time count;
- and
- a time tracker unit coupled to said load store unit, said time tracker unit being adapted to track an actual level 2 cache response time and to adjust said predicted latency time for subsequent accesses to said level 2 cache.
Dependencies are inferred from the claim text.