Partial-address-translation-invalidation request

A method comprising:

• storing, in each of a plurality of cache entries of an address translation cache, address translation data dependent on one or more page table entries of a multi-level page table structure in memory, wherein each page table entry of the multi-level page table structure is useable as at least one of:
• a branch page table entry that specifies a table address of a next level page table;
• and
• a leaf page table entry that specifies an output address for an address translation mapping for a corresponding region of address space;
• and
• in response to a partial-address-translation-invalidation request:
• performing an invalidation lookup operation to identify whether a given cache entry of the address translation cache is a target cache entry to be invalidated, wherein the target cache entry comprises a cache entry for which the address translation data comprises partial address translation data indicative of an address of the next level page table specified by the table address of a target page table entry when used as the branch page table entry;
• and
• triggering an invalidation of the given cache entry when the given cache entry is identified to be the target cache entry,
• said partial-address-translation-invalidation request indicating that the given cache entry is permitted to be retained when the given cache entry provides full address translation data indicative of an address of the corresponding region of address space corresponding to the output address specified by the target page table entry when used as the leaf page table entry.

A non-transitory computer-readable storage medium storing a computer program comprising instructions which, when executed on a host data processing apparatus, control the host data processing apparatus to provide:

• address translation program logic to perform address translations based on a multi-level page table structure in memory, the address translation logic being configured to maintain an address translation data structure comprising a plurality of data structure entries, each data structure entry to store address translation data dependent on one or more page table entries of the multi-level page table structure, wherein each page table entry of the multi-level page table structure is useable as at least one of:
• a branch page table entry that specifies a table address of a next level page table entry;
• and
• a leaf page table entry that specifies an output address for an address translation mapping for a corresponding region of address space;
• and
• control program logic responsive to a partial-address-translation-invalidation request to:
• perform an invalidation lookup operation to identify whether a given data structure entry of the address translation data structure is a target data structure entry to be invalidated, wherein the target data structure entry comprises a data structure entry for which the address translation data comprises partial address translation data indicative of an address of the next level page table specified by the table address of a target page table entry when used as the branch page table entry;
• and
• trigger an invalidation of the given data structure entry when the given data structure entry is identified to be the target data structure entry,
• said partial-address-translation-invalidation request indicating that the given data structure entry is permitted to be retained when the given data structure entry provides full address translation data indicative of an address of the corresponding region of address space corresponding to the output address specified by the target page table entry when used as the leaf page table entry.