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US 2023/0409478 A1Published application
Method and apparatus to reduce latency of a memory-side cache
AssigneeIntel Corporation
InventorsKermin CHOFLEMING, Yu BAI, Simon C. STEELY, JR.
Life of this patent
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Abstract
Latency on the miss path to a cache level in a CPU module is reduced by predicting when a cache miss is likely. Main memory is directly accessed in parallel with the access to the cache level in the CPU module based on the prediction that a cache miss is likely in the cache level.
Claims20
An apparatus comprising:
- a multi-level cache memory;
- and
- a core, the core including a core-side predictor, the core-side predictor to track a hit rate for an instruction pointer in a cache level of the multi-level cache memory to predict a cache miss in the cache level, the core to directly access a memory and the cache level of the multi-level cache memory in parallel based on a prediction that the cache miss is likely in the cache level.
A system comprising:
- a memory;
- and
- a System-on-Package communicatively coupled to the memory, the System-on-Package comprising:
- a multi-level cache memory;
- and
- a core, the core including a core-side predictor, the core-side predictor to track a hit rate for an instruction pointer in a cache level of the multi-level cache memory to predict a cache miss in the cache level, the core to directly access the memory and the cache level of the multi-level cache memory in parallel based on a prediction that the cache miss is likely in the cache level.
3 more elements
A method comprising:
- tracking, by a core-side predictor in a core, a hit rate for an instruction pointer in a cache level of a multi-level cache memory to predict a cache miss in the cache level;
- and
- directly accessing, by the core, a memory and the cache level of the multi-level cache memory in parallel based on a prediction that the cache miss is likely in the cache level.
Dependencies are inferred from the claim text.