# US 2023/0409470 A1 · Scratchpad cache for gaming and iot hosts > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0409470 A1 - Document ID: US20230409470A1 - Status: Published application - Kind: A1 - Application number: 17/841,378 - Filed: 2022-06-15 - Published: 2023-12-21 - Earliest claimed: 2022-06-15 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Ramanathan MUTHIAH - Web page: https://patentgrep.com/patent/US20230409470A1 ## CPC - G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0871: Allocation or management of cache space - G06F 13/1642: {with request queuing} - G06F 13/1668: {Details of memory controller} - G06F 2212/1016: Performance improvement - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Aspects of a data storage device are provided that optimize utilization of a scratchpad memory. The data storage device includes an NVM and a controller which allocates a memory location of the NVM as scratchpad memory for a host. The controller receives a command including data from a submission queue associated with the scratchpad memory, stores the data in the scratchpad memory, and disables first updates to the L2P mapping table for the data in the scratchpad memory across power cycles. The controller also receives commands from other submission queues for other memory locations than the scratchpad memory, stores data in the other memory locations, and stores second updates to a L2P mapping table. The first and second updates may include different data lengths. Thus, the device accounts for differences between scratchpad memory and NVM in at least data alignment, L2P granularity, and response, resulting in efficient scratchpad memory management. ## Claims ### Claim 1 A data storage device, comprising: non-volatile memory (NVM) including a first memory location and a second memory location; and one or more processors coupled to the NVM, the one or more processors, individually or in combination, configured to: allocate the first memory location of the NVM as scratchpad memory for a host; store first data from the host in the scratchpad memory; disable a first update to a logical-to-physical (L2P) mapping table for the first data in the scratchpad memory; store second data from the host in the second memory location; and store a second update to the L2P mapping table for the second data in the second memory location; wherein the first update includes a first amount of data in a first L2P entry for the stored first data and the second update includes a second amount of data in a second L2P entry for the stored second data different than the first amount of data, the first amount of data being a first L2P granularity of the stored first data, and the second amount of data being a second L2P granularity of the stored second data. ### Claim 2 (depends on 1) The data storage device of claim 1, wherein a data length of the first data is at least one sector of the NVM. ### Claim 3 (depends on 2) The data storage device of claim 2, wherein the first data is data segregated from other host data; wherein a data length of the other host data is less than one sector of the NVM; wherein the first data is associated with a lower quality of service (QoS) than the other host data. ### Claim 4 (depends on 1) The data storage device of claim 1, wherein the one or more processors, individually or in combination, are further configured to receive an indication from the host of the first L2P granularity for the first update. ### Claim 5 (depends on 1) The data storage device of claim 1, wherein the one or more processors, individually or in combination, are further configured to: store third data from the host in the scratchpad memory; and disable a third update to the L2P mapping table for the third data in the scratchpad memory; and wherein the third data is associated with a different application program than the first data; wherein the third update includes a third L2P granularity of the stored third data that is different than the first L2P granularity of the first update. ### Claim 6 (depends on 5) The data storage device of claim 5, wherein the one or more processors, individually or in combination, are further configured to receive an indication from the host of the first L2P granularity for the first update and the third L2P granularity for the third update. ### Claim 7 (depends on 5) The data storage device of claim 5, wherein the one or more processors, individually or in combination, are further configured to associate the third L2P granularity of the third update with an application program associated with the third data in response to a host write pattern of other data associated with the application program. ### Claim 8 (depends on 1) The data storage device of claim 1, wherein the one or more processors, individually or in combination, are further configured to: allocate a first region and a second region of the scratchpad memory; store the first data in the first region of the scratchpad memory; store third data in the second region of the scratchpad memory; and disable a third update to the L2P mapping table for the third data in the scratchpad memory; wherein the third update includes a third L2P granularity of the stored third data that is different than the first L2P granularity of the first update. ### Claim 9 (depends on 8) The data storage device of claim 8, wherein the first region and the second region are associated with different hosts. ### Claim 10 (depends on 8) The data storage device of claim 8, wherein the third data is associated with an application program; wherein the one or more processors, individually or in combination, are further configured to associate the third L2P granularity of the third update with the second region of the scratchpad memory in response to a host write pattern of other data associated with the application program. ### Claim 11 (depends on 1) The data storage device of claim 1, wherein the one or more processors, individually or in combination, are further configured to: receive a first command including the first data from a first submission queue associated with the scratchpad memory, the first submission queue including requests for volatile data; and receive a second command including the second data from a second submission queue associated with the NVM, the second submission queue including requests for non-volatile data. ### Claim 12 A data storage device, comprising: non-volatile memory (NVM) including a first memory location and a second memory location; and one or more processors coupled to the NVM, the one or more processors, individually or in combination, configured to: allocate the first memory location of the NVM as scratchpad memory for a host; receive a first command including first data from a first submission queue associated with the scratchpad memory, the first submission queue including requests for volatile data; store the first data in the scratchpad memory; disable an update to a logical-to-physical (L2P) mapping table for the first data in the scratchpad memory; receive a second command including second data from a second submission queue associated with the NVM, the second submission queue including requests for non-volatile data; and store the second data in the second memory location. ### Claim 13 (depends on 12) The data storage device of claim 12, wherein the one or more processors, individually or in combination, are further configured to receive a third command including third data from a third submission queue associated with the scratchpad memory, the third submission queue including other requests for volatile data; wherein the first submission queue and the third submission queue are associated with different hosts. ### Claim 14 (depends on 12) The data storage device of claim 12, wherein the one or more processors, individually or in combination, are further configured to receive a third command including third data from a third submission queue associated with the scratchpad memory, the third submission queue including other requests for volatile data; wherein the first submission queue is associated with a different weightage than the third submission queue. ### Claim 15 (depends on 12) The data storage device of claim 12, wherein the first submission queue is associated with a greater weightage than a weightage of the second submission queue. ### Claim 16 (depends on 12) The data storage device of claim 12, wherein the one or more processors, individually or in combination, are further configured to: allocate a first region and a second region of the scratchpad memory; and receive a third command including third data from a third submission queue associated with the scratchpad memory, the third submission queue including other requests for volatile data; wherein the first submission queue is associated with the first region and the third submission queue is associated with the second region. ### Claim 17 (depends on 12) The data storage device of claim 12, wherein the one or more processors, individually or in combination, are further configured to: receive a third command including third data from a third submission queue associated with the scratchpad memory, the third submission queue including other requests for volatile data; and disable another update to the L2P mapping table for the third data in the scratchpad memory; and wherein the update includes a first L2P granularity of the stored first data and the another update includes a second L2P granularity of the stored second data different than the first L2P granularity; wherein the first submission queue is associated with the first L2P granularity and the third submission queue is associated with the second L2P granularity. ### Claim 18 (depends on 17) The data storage device of claim 17, wherein the one or more processors, individually or in combination, are further configured to allocate a first region and a second region of the scratchpad memory; wherein the first L2P granularity is associated with the first region and the second L2P granularity is associated with the second region. ### Claim 19 (depends on 18) The data storage device of claim 18, wherein the first region is associated with a different host than that of the second region. ### Claim 20 A data storage device, comprising: non-volatile memory (NVM) including a first memory location and a second memory location; means for allocating the first memory location of the NVM as scratchpad memory for a host; means for receiving a first command including first data from a first submission queue associated with the scratchpad memory and a second command including second data from a second submission queue associated with the NVM, the first submission queue including requests for volatile data and the second submission queue including requests for non-volatile data; means for storing the first data in the scratchpad memory, the second data in the second memory location, and an update to a logical-to-physical (L2P) mapping table for the second data in the second memory location; and means for disabling another update to the L2P mapping table for the first data in the scratchpad memory; wherein the update includes a first amount of data in a first L2P entry for the stored first data and the another update includes a second amount of data in a second L2P entry for the stored second data different than the first amount of data, the first amount of data being a first L2P granularity of the stored first data, and the second amount of data being a second L2P granularity of the stored second data.