Computational memory
AssigneeUntether Ai Corporation
InventorsWilliam Martin SNELGROVE, Darrick John WIEBE
Life of this patent
Estimating the term…
Abstract
An example device includes a plurality of computational memory banks. Each computational memory bank of the plurality of computational memory banks includes an array of memory units and a plurality of processing elements connected to the array of memory units. The device further includes a plurality of single instruction, multiple data (SIMD) controllers. Each SIMD controller of the plurality of SIMD controllers is contained within at least one computational memory bank of the plurality of computational memory banks. Each SIMD controller is to provide instructions to the at least one computational memory bank.
Claims21
1-23. (canceled)
A device comprising:
- a plurality of computational memory banks, each computational memory bank of the plurality of computational memory banks including an array of memory units and a plurality of processing elements connected to the array of memory units;
- and
- a plurality of single instruction, multiple data (SIMD) controllers, each SIMD controller of the plurality of SIMD controllers being contained within at least one computational memory bank of the plurality of computational memory banks;
- wherein each SIMD controller is to provide instructions to the at least one computational memory bank and control execution of the instructions by the at least one computational memory bank;
- wherein each processing element of the plurality of processing elements includes registers and an arithmetic logic unit (ALU) to perform operations with the registers;
- and
- wherein each processing element of the plurality of processing elements is to receive communicated state from registers of another processing element, the ALU to perform operations with the registers and the communicated state.
A device comprising:
- a plurality of computational memory banks, each computational memory bank of the plurality of computational memory banks including an array of memory units and a plurality of processing elements connected to the array of memory units;
- and
- a plurality of single instruction, multiple data (SIMD) controllers, each SIMD controller of the plurality of SIMD controllers being contained within at least one computational memory bank of the plurality of computational memory banks;
- wherein each SIMD controller is to provide instructions to the at least one computational memory bank and control execution of the instructions by the at least one computational memory bank;
- and
- wherein each processing element of the plurality of processing elements includes registers, and an arithmetic logic unit (ALU) to perform operations with the registers, and communications registers that are slaved to the registers, the communications registers to provide communicated state to another processing element.
Dependencies are inferred from the claim text.