Providing code sections for matrix of arithmetic logic units in a processor

A data processor comprising:

• an execution stage for processing data having a plurality of ALUs in a multidimensional array, adapted to process data according to instructions that are issued thereto, with at least some of the plurality of ALUs at least having an operand data input and a result data output, and the multidimensional array having a data network at least interconnecting the at least some of the plurality of ALUs for providing operand data to the at least some of the plurality of ALUs, result data generated by the at least some of the plurality of ALUs when executing amended instructions issued thereto being provided to the data network;
• an instruction fetch unit to fetch instructions,
• at least some of the instructions fetched by said instruction fetch unit being executable to process operand data to produce result data, wherein the operand data has at least one operand source register reference and the result data has at least one target register reference, and
• the at least some of the instructions forming a sequence of instructions, wherein at least some of the result data produced in response to preceding instructions in the sequence of instructions is used as operand data in succeeding instructions in the sequence of instructions;
• an instruction issue unit to issue amended instructions at least to the execution stage, for executing at least some of the amended instructions by at least some of the plurality of ALUs,
• the at least some of the plurality of ALUs generating the result data from the operand data by execution of the at least some of amended instructions issued by the instruction issue unit;
• and
• an instruction amendment unit comprising
• a register cross referencing table that cross-references target register references of the fetched instructions to the ALUs in the multidimensional array producing the result data corresponding to said target register references of the fetched instructions,
• wherein, for instructions of the sequence of instructions that use result data generated in response to preceding instructions as operand data, the instruction amendment unit is adapted to look up, in the register cross referencing table, the ALUs in the multidimensional array that execute the respective preceding instructions that generate the result data corresponding to said target register references of the fetched instructions,
• the instruction amendment unit generating amended instructions and providing the amended instructions to the instruction issue unit, the instruction amendment unit generating the amended instructions based on the fetched sequence of instructions and based on the result of the look-up,
• such that when the amended instructions are issued by the instruction issue unit and executed by the execution stage, the result data generated by ALUs executing preceding instructions issued by the instruction issue unit are transferred in the data network in a manner enabling the use thereof as operand data in the succeeding instructions issued by the instruction issue unit.

A method comprising:

• fetching instructions using an instruction fetch unit,
• at least some of the instructions fetched by said instruction fetch unit being executable, when issued thereto, by a plurality of ALUs in a multidimensional array of an execution stage to process operand data to produce result data, wherein the operand data has at least one operand source register reference and the result data has at least one target register reference, and
• the at least some of the instructions forming a sequence of instructions, wherein at least some of the result data produced in response to executing preceding instructions in the sequence of instructions is used as operand data in executing succeeding instructions in the sequence of instructions;
• providing the operand data to at least some of the plurality of ALUs using a data network of the multidimensional array that interconnects the plurality of ALUs, wherein the result data generated by the at least some of the plurality of ALUs when executing the instructions are provided to the data network;
• and
• accessing, using an instruction amendment unit, a register cross referencing table that cross references target register references of the fetched instructions to the ALUs in the multidimensional array producing the result data corresponding to said target register references of the fetched instructions,
• wherein, for instructions of the sequence of instructions that use result data generated in response to preceding instructions as operand data, accessing the register cross referencing table includes looking up, in the register cross referencing table, the ALUs in the multidimensional array that execute the respective preceding instructions that generate the result data corresponding to said target register references of the fetched instructions;
• generating, using the instruction amendment unit, amended instructions based on the fetched sequence of instructions and based on the result of the look-up;
• providing, by the instruction amendment unit, the amended instructions to an instruction issue unit;
• issuing, by the instruction issue unit, amended instructions at least to the execution stage;
• and
• executing at least some of the amended instructions issued by the instruction issue unit by at least some of the plurality of ALUs of the execution stage, wherein the at least some of the plurality of ALUs have at least an operand data input and a result data output, wherein the at least some of the plurality of ALUs generate the result data from the operand data by execution of the at least some of amended instructions issued by the instruction issue unit,
• such that when the amended instructions are issued by the instruction issue unit and executed by the execution stage, the result data generated by ALUs executing preceding instructions issued by the issue unit are transferred in the data network in a manner enabling the use thereof as operand data in the succeeding issued by the issue unit.