# US 2023/0409333 A1 · Instructions and support for calculating prefix sums > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0409333 A1 - Document ID: US20230409333A1 - Status: Published application - Kind: A1 - Application number: 17/843,823 - Filed: 2022-06-17 - Published: 2023-12-21 - Earliest claimed: 2022-06-17 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Menachem ADELMAN; Amit GRADSTEIN; Regev SHEMY; Chitra NATARAJAN; Igor ERMOLAEV - Web page: https://patentgrep.com/patent/US20230409333A1 ## CPC - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/3001: {Arithmetic instructions} - G06F 9/30038: {using a mask} - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques for performing prefix sums in response to a single instruction are describe are described. In some examples, the single instruction includes fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least: perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand. ## Claims ### Claim 1 An apparatus comprising: decoder circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least: perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand; and execution circuitry configured to execute the decoded instruction according to the opcode. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the one or more fields to reference the first source operand identify a vector register. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the one or more fields to reference the first source operand identify a vector register identify a memory location. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein packed data elements of the first and second sources are of a datatype unsigned integer, signed integer, and floating point. ### Claim 5 (depends on 5) The apparatus of claim 5, wherein packed data elements of the first and second sources are 8-bit, 16-bit, 32-bit, or 64-bit in size. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the instance of the single instruction further comprises a field for a prefix, wherein the prefix provides one or more fields to reference a mask operand and one or more bits to be used to reference the at least one of the sources. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the execution circuitry is to use the mask operand to determine which data element positions of the destination operand to write. ### Claim 8 (depends on 6) The apparatus of claim 6, the execution circuitry is to use the mask operand to determine which data element positions of the second source to unmask. ### Claim 9 A method comprising: decoding an instance of a single instruction, the single instruction including fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least: perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand; and executing the decoded instruction according to the opcode. ### Claim 10 (depends on 9) The method of claim 9, wherein the one or more fields to reference the first source operand identify a vector register. ### Claim 11 (depends on 9) The method of claim 9, wherein the one or more fields to reference the first source operand identify a vector register identify a memory location. ### Claim 12 (depends on 9) The method of claim 9, wherein packed data elements of the first and second sources are of a datatype unsigned integer, signed integer, and floating point. ### Claim 13 (depends on 12) The method of claim 12, wherein packed data elements of the first and second sources are 8-bit, 16-bit, 32-bit, or 64-bit in size. ### Claim 14 (depends on 9) The method of claim 9, wherein the instance of the single instruction further comprises a field for a prefix, wherein the prefix provides one or more fields to reference a mask operand and one or more bits to be used to reference the at least one of the sources. ### Claim 15 (depends on 14) The method of claim 14, wherein the executing is to use the mask operand to determine which data element positions of the destination operand to write. ### Claim 16 (depends on 14) The method of claim 14, the executing is to use the mask operand to determine which data element positions of the second source to unmask. ### Claim 17 A method comprising: translating an instance of a single instruction of a first instruction set architecture to one or more instructions of a second instruction set architecture, the single instruction including fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least: perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand; and decoding the one or more instructions of the second instruction set architecture; executing the decoded one or more instructions of the second instruction set architecture instruction according to the opcode of the single instruction of the first instruction set architecture. ### Claim 18 (depends on 17) The method of claim 17, wherein the one or more fields to reference the first source operand identify a vector register. ### Claim 19 (depends on 17) The method of claim 17, wherein the one or more fields to reference the first source operand identify a vector register identify a memory location. ### Claim 20 (depends on 17) The method of claim 17, wherein packed data elements of the first and second sources are of a datatype unsigned integer, signed integer, and floating point. ### Claim 21 (depends on 20) The method of claim 20, wherein packed data elements of the first and second sources are 8-bit, 16-bit, 32-bit, or 64-bit in size. ### Claim 22 (depends on 21) The method of claim 21, wherein the instance of the single instruction further comprises a field for a prefix, wherein the prefix provides one or more fields to reference a mask operand and one or more bits to be used to reference the at least one of the sources. ### Claim 23 (depends on 22) The method of claim 22, wherein the executing is to use the mask operand to determine which data element positions of the destination operand to write. ### Claim 24 (depends on 22) The method of claim 22, the executing is to use the mask operand to determine which data element positions of the second source to unmask. ### Claim 25 A system comprising: memory to store an instance of a single instruction; and a processor core comprising: decoder circuitry to decode an instance of the single instruction, the single instruction to include fields for an opcode, one or fields to reference a first source operand, one or fields to reference a second source operand, one or fields to reference a destination operand, wherein the opcode is to indicate that execution circuitry is, in response to a decoded instance of the single instruction, to at least: perform a prefix sum by for each non-masked data element position of the second source operand adding a data element of that data element position to each data element of preceding data element positions and adding at least one data element of a defined data element position of the first source operand, and store each prefix sum for each data element position of the second source operand into a corresponding data element position of the destination operand; and execution circuitry configured to execute the decoded instruction according to the opcode.