# US 2023/0409331 A1 · Load reissuing using an alternate issue queue

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- Number: US 2023/0409331 A1
- Document ID: US20230409331A1
- Status: Published application
- Kind: A1
- Application number: 17/807,243
- Filed: 2022-06-16
- Published: 2023-12-21
- Earliest claimed: 2022-06-16
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Jonathan Ting Hsieh; Gregory William Alexander; Aaron Tsai; Yossi Shapira
- Web page: https://patentgrep.com/patent/US20230409331A1

## CPC

- G06F 9/3808: {for instruction reuse, e.g. trace cache, branch target cache}
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/3802: {Instruction prefetching}
- G06F 9/3824: {Operand accessing}
- G06F 9/3834: {Maintaining memory consistency}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags}
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1024: Latency reduction
- G06F 2212/452: Instruction code
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In an approach, responsibility for reissuing a fetch micro-operation is allocated to a reissue queue subsequent to a cache miss corresponding to a cache and the fetch micro-operation. Responsive to higher level cache returning data to the cache, an issue selection algorithm of the issue queue is overridden to prioritize reissuing the fetch micro-operation.

## Claims

### Claim 1

A computer-implemented method comprising:
subsequent to a cache miss corresponding to a cache and a fetch micro-operation issuing from an issue queue, allocating responsibility for reissuing the fetch micro-operation to a reissue queue; and
responsive to higher level cache returning data to the cache, overriding an issue selection algorithm of the issue queue to prioritize reissuing the fetch micro-operation.

### Claim 2 (depends on 1)

The computer-implemented method of claim 1, wherein allocating responsibility for reissuing the fetch micro-operation to the reissue queue comprises:
setting a valid bit of an entry of the reissue queue; and
setting remaining fields of the entry with information corresponding to the fetch micro-operation.

### Claim 3 (depends on 2)

The computer-implemented method of claim 2, wherein the remaining fields comprise an issue queue position field, an issue pipe identifier field, a micro-operation tag field, a micro-operation thread identifier (ID) field, and a data ID field.

### Claim 4 (depends on 3)

The computer-implemented method of claim 3, further comprising:
receiving a data ID from a cache return; and
determining (i) the data ID matches the data ID field of the entry and (ii) the valid bit of the entry is set.

### Claim 5 (depends on 3)

The computer-implemented method of claim 3, wherein overriding the issue selection algorithm of the issue queue to prioritize reissuing the fetch micro-operation comprises:
overriding micro-operation issuance from an issue pipe specified by the issue pipe identifier field of the entry; and
indexing the issue queue at a position specified by the issue queue position field.

### Claim 6 (depends on 1)

The computer-implemented method of claim 1, wherein reissuing the fetch micro-operation comprises:
reading the data by bypassing pipeline latch data around the cache, wherein reading the data occurs prior to writing the data to the cache.

### Claim 7 (depends on 4)

The computer-implemented method of claim 4, wherein the data ID from the cache return is associated with a smallest granularity of data returned by the higher level cache.

### Claim 8

A computer program product comprising:
one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instructions comprising:
program instructions to, subsequent to a cache miss corresponding to a cache and a fetch micro-operation issuing from an issue queue, allocate responsibility for reissuing the fetch micro-operation to a reissue queue; and
program instructions to, responsive to higher level cache returning data to the cache, override an issue selection algorithm of the issue queue to prioritize reissuing the fetch micro-operation.

### Claim 9 (depends on 8)

The computer program product of claim 8, wherein program instructions to allocate responsibility for reissuing the fetch micro-operation to the reissue queue comprise:
program instructions to set a valid bit of an entry of the reissue queue; and
program instructions to set remaining fields of the entry with information corresponding to the fetch micro-operation.

### Claim 10 (depends on 9)

The computer program product of claim 9, wherein the remaining fields comprise an issue queue position field, an issue pipe identifier field, a micro-operation tag field, a micro-operation thread identifier (ID) field, and a data ID field.

### Claim 11 (depends on 10)

The computer program product of claim 10, further comprising:
program instructions, collectively stored on the one or more computer readable storage media, to receive a data ID from a cache return; and
program instructions, collectively stored on the one or more computer readable storage media, to determine (i) the data ID matches the data ID field of the entry and (ii) the valid bit of the entry is set.

### Claim 12 (depends on 10)

The computer program product of claim 10, wherein program instructions to override the issue selection algorithm of the issue queue to prioritize reissuing the fetch micro-operation comprise:
program instructions to override micro-operation issuance from an issue pipe specified by the issue pipe identifier field of the entry; and
program instructions to index the issue queue at a position specified by the issue queue position field.

### Claim 13 (depends on 8)

The computer program product of claim 8, wherein program instructions to reissue the fetch micro-operation comprise:
program instructions to read the data by bypassing pipeline latch data around the cache, wherein reading the data occurs prior to writing the data to the cache.

### Claim 14 (depends on 4)

The computer program product of claim 4, wherein the data ID from the cache return is associated with a smallest granularity of data returned by the higher level cache.

### Claim 15

A computer system comprising:
one or more computer processors, one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media for execution by at least one of the one or more computer processors, the program instructions comprising:
program instructions to, subsequent to a cache miss corresponding to a cache and a fetch micro-operation issuing from an issue queue, allocate responsibility for reissuing the fetch micro-operation to a reissue queue; and
program instructions to, responsive to higher level cache returning data to the cache, override an issue selection algorithm of the issue queue to prioritize reissuing the fetch micro-operation.

### Claim 16 (depends on 15)

The computer system of claim 15, wherein program instructions to allocate responsibility for reissuing the fetch micro-operation to the reissue queue comprise:
program instructions to set a valid bit of an entry of the reissue queue; and
program instructions to set remaining fields of the entry with information corresponding to the fetch micro-operation.

### Claim 17 (depends on 16)

The computer system of claim 16, wherein the remaining fields comprise an issue queue position field, an issue pipe identifier field, a micro-operation tag field, a micro-operation thread identifier (ID) field, and a data ID field.

### Claim 18 (depends on 17)

The computer system of claim 17, further comprising:
program instructions, collectively stored on the one or more computer readable storage media for execution by at least one of the one or more computer processors, to receive a data ID from a cache return; and
program instructions, collectively stored on the one or more computer readable storage media for execution by at least one of the one or more computer processors, to determine (i) the data ID matches the data ID field of the entry and (ii) the valid bit of the entry is set.

### Claim 19 (depends on 17)

The computer system of claim 17, wherein program instructions to override the issue selection algorithm of the issue queue to prioritize reissuing the fetch micro-operation comprise:
program instructions to override micro-operation issuance from an issue pipe specified by the issue pipe identifier field of the entry; and
program instructions to index the issue queue at a position specified by the issue queue position field.

### Claim 20 (depends on 15)

The computer system of claim 15, wherein program instructions to reissue the fetch micro-operation comprise:
program instructions to read the data by bypassing pipeline latch data around the cache, wherein reading the data occurs prior to writing the data to the cache.