System for error detection and correction in a multi-thread processor

A multi-thread processor, including:

• a master processor configured to execute at least a plurality of threads, with at least a first thread and a second thread designated to run a program in sequence;
• a slave processor configured to execute at least a third thread, with the third thread designated to run the program in sequence;
• and
• an instruction fetch compare engine;
• wherein, the first thread of the master processor configured to
• initiate a first thread instruction fetch for the program, the first thread instruction fetch for the program stored in an instruction fetch storage;
• retrieve data associated with the fetched first thread instruction;
• and
• store the retrieved data associated with the fetched first thread instruction in a retrieved data storage;
• wherein, the second thread of the master processor configured to
• initiate a second thread instruction fetch for the program;
• and
• wherein, the instruction fetch compare logic compares the second thread instruction fetch for the program with the first thread instruction fetch stored in the instruction fetch storage for a match;
• and
• when there is a match, present the retrieved data associated with the fetched first thread instruction from the retrieved data storage, in response to the second thread instruction fetch for the program.