Parallel processing architecture with memory block transfers

A computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to perform operations of:

• accessing an array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
• providing control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide control words generated by the compiler;
• and
• executing a memory block transfer, wherein the memory block transfer is initiated by a control word from the stream of wide control words, and wherein data for the memory block transfer is moved independently from the array of compute elements.

A computer system for task processing comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access an array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
• provide control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide control words generated by the compiler;
• and
• execute a memory block transfer, wherein the memory block transfer is initiated by a control word from the stream of wide control words, and wherein data for the memory block transfer is moved independently from the array of compute elements.