Apparatus and method for performing accumulation operations

A method, comprising:

• performing, using processing circuitry, an accumulation operation in which a first addend is added to a second addend to produce an updated second addend;
• and
• storing the second addend in a plurality of lanes within storage circuitry, each lane storing a plurality of contiguous bits of the second addend, and each lane having a significance different to that of each other lane, wherein a more significant lane has at least one bit with a higher bit significance than the most significant bit of a less significant lane;
• wherein each lane within at least a subset of the plurality of lanes comprises at least one overlap bit, each overlap bit having the same bit significance as a bit in an adjacent more significant lane in the plurality of lanes;
• wherein the accumulation operation is performed by the processing circuitry by:
• referencing bit significance information corresponding to the first addend to select an accumulating lane out of the plurality of lanes;
• and
• performing an addition operation between bits of the accumulating lane and the first addend.

A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising:

• processing circuitry configured to perform an accumulation operation in which a first addend is added to a second addend to produce an updated second addend;
• and
• storage circuitry configured to store the second addend in a plurality of lanes, each lane storing a plurality of contiguous bits of the second addend, and each lane having a significance different to that of each other lane, wherein a more significant lane has at least one bit with a higher bit significance than the most significant bit of a less significant lane;
• wherein each lane within at least a subset of the plurality of lanes comprises at least one overlap bit, each overlap bit having the same bit significance as a bit in an adjacent more significant lane in the plurality of lanes;
• wherein the processing circuitry is arranged to perform the accumulation operation by:
• referencing bit significance information corresponding to the first addend to select an accumulating lane out of the plurality of lanes;
• and
• performing an addition operation between bits of the accumulating lane and the first addend.