# US 2023/0409284 A1 · Method and apparatus for use in the design and manufacture of integrated circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0409284 A1 - Document ID: US20230409284A1 - Status: Published application - Kind: A1 - Application number: 18/241,977 - Filed: 2023-09-04 - Published: 2023-12-21 - Earliest claimed: 2011-10-06 - Assignees: Imagination Technologies Limited - Applicants: Imagination Technologies Limited - Inventors: Theo Alan Drane; Wai-Chuen Cheung - Web page: https://patentgrep.com/patent/US20230409284A1 ## CPC - G06F 7/38: Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation - G06F 7/535: Dividing only - G06F 30/00: Computer-aided design [CAD] - G06F 30/30: Circuit design - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived. ## Claims ### Claim 1 A computer-implemented method for generating a representation of an integrated circuit for performing integer division x/d where x is a variable integer and d is an invariant integer constant, the method comprising: deriving, using a parameter creator, an integer triple (a,b,k) which satisfies Round(x/d)=(ax+b)/2k for a desired rounding mode; and generating, using a synthesis tool, the representation of the integrated circuit for manufacture of the integrated circuit, wherein the representation of the integrated circuit is generated using a representation of the logical operation (ax+b)/2k in accordance with the derived integer triple (a,b,k). ### Claim 2 (depends on 1) The method of claim 1, wherein deriving the integer triple (a,b,k) comprises deriving an integer triple (a,b,k) which has a minimum value of k to satisfy Round(x/d)=(ax+b)/2k for the desired rounding mode. ### Claim 3 (depends on 1) The method of claim 1, further comprising deriving, using a representation generator, the representation of the logical operation (ax+b)/2k using the derived integer triple (a,b,k). ### Claim 4 (depends on 1) The method of claim 1, wherein the representation of the logical operation (ax+b)/2k is an RTL (Register Transfer Level) representation. ### Claim 5 (depends on 1) The method of claim 1, wherein the desired rounding mode is one of: (i) round towards zero, (ii) round to nearest, and (iii) faithful rounding. ### Claim 6 (depends on 1) The method of claim 1, wherein deriving the integer triple (a,b,k) comprises deriving a value for b from values of k and a in which the derived value of b has the smallest Hamming weight of the possible values of b satisfying Round(x/d)=(ax+b)/2k. ### Claim 7 (depends on 1) The method of claim 1, further comprising manufacturing the integrated circuit from the representation of the integrated circuit. ### Claim 8 (depends on 1) The method of claim 1, wherein the derivation of k is different for different rounding modes. ### Claim 9 A non-transitory computer readable medium having stored thereon computer executable instructions that when executed cause at least one processor to: derive, using a parameter creator, an integer triple (a,b,k) which satisfies Round(x/d)=(ax+b)/2k for a desired rounding mode where x is a variable integer and d is an invariant integer constant; and generate, using a synthesis tool, a representation of an integrated circuit for performing integer division xl d from a representation of the logical operation (ax+b)/2k in accordance with the derived integer triple (a,b,k) for manufacture of the integrated circuit. ### Claim 10 (depends on 9) The non-transitory computer readable medium of claim 9, wherein execution of the executable instructions cause the at least one processor to derive an integer triple (a,b,k) which has a minimum value of k to satisfy Round(x/d)=(ax+b)/2k for the desired rounding mode. ### Claim 11 (depends on 9) The non-transitory computer readable medium of claim 9, wherein execution of the executable instructions cause the at least one processor to derive, using a representation generator, the representation of the logical operation (ax+b)/2k using the derived integer triple (a,b,k). ### Claim 12 (depends on 9) The non-transitory computer readable medium of claim 9, wherein the representation of the logical operation (ax+b)/2k is an RTL (Register Transfer Level) representation. ### Claim 13 (depends on 9) The non-transitory computer readable medium of claim 9, wherein the desired rounding mode is one of: (i) round towards zero, (ii) round to nearest, and (iii) faithful rounding. ### Claim 14 (depends on 9) The non-transitory computer readable medium of claim 9, wherein deriving the integer triple (a,b,k) comprises deriving a value for b from values of k and a in which the derived value of b has the smallest Hamming weight of the possible values of b satisfying Round(x/d)=(ax+b)/2k. ### Claim 15 (depends on 9) The non-transitory computer readable medium of claim 9, wherein the derivation of k is different for different rounding modes. ### Claim 16 A method of manufacturing, using an integrated circuit manufacturing system, an integrated circuit for performing integer division, the method comprising: processing, using a layout processing system, a representation of an integrated circuit for performing integer division xl d where x is a variable integer and d is an invariant integer constant so as to generate a circuit layout description of an integrated circuit for performing integer division, the representation of the integrated circuit for performing integer division being generated in accordance with a method comprising: deriving, using a parameter creator, an integer triple (a,b,k) which satisfies Round(x/d)=(ax+b)/2k for a desired rounding mode, and generating, using a synthesis tool, the representation of the integrated circuit for manufacture of the integrated circuit, wherein the representation of the integrated circuit is generated using a representation of the logical operation (ax+b)/2k in accordance with the derived integer triple (a,b,k); and manufacturing, using an integrated circuit generation system, the integrated circuit for performing integer division according to the circuit layout description.