# US 2023/0409104 A1 · Efficient system on chip power delivery with adaptive voltage headroom control > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0409104 A1 - Document ID: US20230409104A1 - Status: Published application - Kind: A1 - Application number: 17/845,677 - Filed: 2022-06-21 - Published: 2023-12-21 - Earliest claimed: 2022-06-21 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Alexander LYAKHOV; Piyush Abhay HATOLKAR; Anant Shankar DEVAL; Juan Pablo MUNOZ CONSTANTINE - Web page: https://patentgrep.com/patent/US20230409104A1 ## CPC - G06F 1/305: {in the event of power-supply fluctuations} - G06F 1/3296: by lowering the supply or operating voltage - G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision - G06F 1/324: by lowering clock frequency - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage. ## Claims ### Claim 1 A system comprising: a system-on-chip (SoC) including a plurality of cores; a voltage regulator module (VRM), based on a voltage set point associated with the VRM, configured to provide an input voltage to each of per core voltage regulators in the SoC, wherein each of the per core voltage regulators is configured to provide an output voltage to a corresponding core from among the plurality of cores; and an adaptive voltage headroom control apparatus including: (1) a voltage controller for controlling the voltage set point associated with the VRM, (2) a per core voltage regulator headroom monitor, (3) a per core droop detector, and (4) a per core frequency controller configured to control a frequency of a core clock signal for a respective core from among the plurality of cores, wherein the adaptive voltage headroom control apparatus is configured to: in response to either a detection of a headroom violation by the per core voltage regulator headroom monitor or a detection of a voltage droop by the per core droop detector, independently throttle operating frequency of a respective core clock signal, and in response to either headroom violation events or droop events meeting a predetermined criterion: (1) lower the operating frequency of the respective core clock signal to a lowered operating frequency, (2) monitor headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion even at the lowered operating frequency, change the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage. ### Claim 2 (depends on 1) The system of claim 1, wherein each of the per core voltage regulators comprises a low-dropout (LDO) regulator, and wherein the headroom violation event corresponds to a headroom violation associated with a respective LDO regulator. ### Claim 3 (depends on 1) The system of claim 1, wherein each of the per core voltage regulators comprises a low-dropout (LDO) regulator, and wherein the voltage droop event corresponds to a droop associated with an output voltage of a respective LDO regulator. ### Claim 4 (depends on 1) The system of claim 1, wherein the adaptive voltage headroom control apparatus is configured to independently throttle frequency of the respective core clock signal by masking the respective core clock signal. ### Claim 5 (depends on 1) The system of claim 1, wherein the adaptive voltage headroom control apparatus is further configured to, having operated the system for a predetermined duration after changing the voltage set point associated with the VRM to the second voltage setpoint associated with the VRM, raise an operating frequency of one or more respective core clock signals. ### Claim 6 (depends on 1) The system of claim 1, wherein the adaptive voltage headroom control apparatus is further configured to, having operated the system for a predetermined duration after changing the voltage set point associated with the VRM to the second voltage setpoint associated with the VRM, lower a headroom associated with one or more per core voltage regulators. ### Claim 7 (depends on 1) The system of claim 1, wherein the per core frequency controller is further configured to monitor a respective core voltage and ramp up throttled operating frequency of a respective core clock signal to an original frequency once the respective core voltage has recovered from the voltage droop. ### Claim 8 A method for adaptively controlling voltage headroom for a system including: (1) a system-on-chip (SoC) including a plurality of cores, and (2) a voltage regulator module (VRM), based on a voltage set point associated with the VRM, configured to provide an input voltage to each of per core voltage regulators in the SoC, wherein each of the per core voltage regulators is configured to provide an output voltage to a corresponding core from among the plurality of cores, the method comprising: in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal; and in response to either headroom violation events or droop events meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal to a lowered operating frequency, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion even at the lowered operating frequency, changing the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage. ### Claim 9 (depends on 8) The method of claim 8, wherein each of the per core voltage regulators comprises a low-dropout (LDO) regulator, and wherein the headroom violation event corresponds to a headroom violation associated with a respective LDO regulator. ### Claim 10 (depends on 8) The method of claim 8, wherein each of the per core voltage regulators comprises a low-dropout (LDO) regulator, and wherein the voltage droop event corresponds to a droop associated with an output voltage of a respective LDO regulator. ### Claim 11 (depends on 8) The method of claim 8, wherein independently throttling frequency of the respective core clock signal comprises masking the respective core clock signal. ### Claim 12 (depends on 8) The method of claim 8, further comprising, having operated the system for a predetermined duration after changing the voltage set point associated with the VRM to the second voltage setpoint associated with the VRM, raising an operating frequency of one or more respective core clock signals. ### Claim 13 (depends on 8) The method of claim 8, further comprising, having operated the system for a predetermined duration after changing the voltage set point associated with the VRM to the second voltage setpoint associated with the VRM, lowering a headroom associated with one or more per core voltage regulators. ### Claim 14 (depends on 8) The method of claim 8, further comprising monitoring a respective core voltage and ramping up throttled operating frequency of a respective core clock signal to an original frequency once the respective core voltage has recovered from the voltage droop. ### Claim 15 A system comprising: a system-on-chip (SoC) including a plurality of cores; a voltage regulator module (VRM), based on a voltage set point associated with the VRM, configured to provide an input voltage to each of per core low-dropout (LDO) voltage regulators in the SoC, wherein each of the per core LDO voltage regulators is configured to provide an output voltage to a corresponding core from among the plurality of cores; and an adaptive voltage headroom control apparatus including: (1) a voltage controller for controlling the voltage set point associated with the VRM, (2) a per core LDO voltage regulator headroom monitor, (3) a per core droop detector, and (4) a per core frequency controller configured to control a frequency of a core clock signal for a respective core from among the plurality of cores, wherein the adaptive voltage headroom control apparatus is configured to: in response to either a detection of a headroom violation by the per core LDO voltage regulator headroom monitor or a detection of a voltage droop by the per core droop detector, independently throttle operating frequency of a respective core clock signal, and in response to either headroom violation events or droop events meeting a predetermined criterion: (1) lower the operating frequency of the respective core clock signal to a lowered operating frequency, (2) monitor headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion even at the lowered operating frequency, change the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage. ### Claim 16 (depends on 15) The system of claim 15, wherein the headroom violation event corresponds to a headroom violation associated with a respective LDO regulator. ### Claim 17 (depends on 15) The system of claim 15, wherein the voltage droop event corresponds to a droop associated with an output voltage of a respective LDO regulator. ### Claim 18 (depends on 15) The system of claim 15, wherein the adaptive voltage headroom control apparatus is configured to independently throttle frequency of the respective core clock signal by masking the respective core clock signal. ### Claim 19 (depends on 15) The system of claim 15, wherein the adaptive voltage headroom control apparatus is further configured to, having operated the system for a predetermined duration after changing the voltage set point associated with the VRM to the second voltage setpoint associated with the VRM, raise an operating frequency of one or more respective core clock signals. ### Claim 20 (depends on 15) The system of claim 15, wherein the adaptive voltage headroom control apparatus is further configured to, having operated the system for a predetermined duration after changing the voltage set point associated with the VRM to the second voltage setpoint associated with the VRM, lower a headroom associated with one or more per core LDO voltage regulators.