Ultra-low power d flip-flop with reduced clock load

A D flip-flop with reduce clock network loading comprising:

• a master latch comprising:
• a first transistor set configured as a switching element, the first transistor set configured to receive one or more clock signals from a clock network and an input signal;
• a second transistor set configured as an inverter, the second transistor set configured to receive the input signal from the first transistor set responsive to the one or more clock signals, and create a master latch output;
• a third transistor set configured to receive a gate voltage that causes transistors in the third transistor set to be weakly on to provide a feedback signal to the second transistor set;
• a fourth transistor set configured as an inverter, wherein at least one of the weakly on transistors in the third transistor set is in series with at least one transistor in the fourth transistor set and the third transistor set and the fourth transistor set do not receive the one or more clock signals;
• a slave latch comprising:
• a fifth transistor set functioning as a switching element, the fifth transistor set configured to receive the one or more clock signals and the master latch output;
• a sixth transistor set functioning as an inverter, the sixth transistor set configured to receive the master latch output from the fifth transistor set responsive to the one or more clock signals, and create a slave latch output;
• a seventh transistor set configured to receive a gate voltage that causes transistors in the seventh transistor set to be weakly on to provide a feedback signal to the sixth transistor set;
• and
• an eighth transistor set configured as an inverter, wherein at least one of the weakly on transistors in the seventh transistor set is in series with at least one transistor in the eighth transistor set and the seventh transistor set and the eighth transistor set do not receive the one or more clock signals.