Drift detection in timing signal forwarded from memory controller to memory device
AssigneeRambus Inc.
InventorsJun Kim, Pak Shing Chau, Wayne S. Richardson
Life of this patent
Estimating the term…
Abstract
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
Claims21
(canceled)
A memory controller comprising:
- a phase lock loop to generate a first timing signal having a first frequency;
- a multiplexor connected to the phase lock loop, the multiplexor to receive the first timing signal from an output of the phase lock loop and a second timing signal having a second frequency that is less than the first frequency, the multiplexor to output one of the first timing signal or the second timing signal;
- an interface circuit connected the multiplexor, the interface circuit to output, to a memory device, one of the first timing signal or the second timing, and the interface circuit to receive from the memory device information indicative of a phase delay, occurring on the second timing signal, associated with timing drift in the memory device;
- and
- a phase mixer circuit connected to the multiplexor, the phase mixer circuit to adjust a phase of the first timing signal based on the information indicative of the phase delay.
A method of operating a memory controller, the method comprising:
- generating, by a phase lock loop of the memory controller, a first timing signal having a first frequency;
- receiving, by a multiplexor connected to the phase lock loop, the first timing signal from the multiplexor and a second timing signal having a second frequency that is less than the first frequency,
- outputting, by an interface circuit connected to the multiplexor, the first timing signal or the second timing signal to a memory device;
- receiving, by the interface circuit, information indicative of a phase delay occurring on the second timing signal associated with timing drift in the memory device;
- and
- adjusting, by a phase mixer circuit, a phase of the first timing signal based on the information indicative of the phase delay occurring on the second timing signal.
A memory controller comprising:
- means for generating a first timing signal having a first frequency;
- means for receiving the first timing signal and a second timing signal, the second timing signal having a second frequency that is less than the first frequency;
- means for outputting the first timing signal or the second timing signal to a memory device;
- and
- means for adjusting a phase of the first timing signal based on information indicative of a phase delay occurring on the second timing signal.
Dependencies are inferred from the claim text.