Memory Arrays Comprising Vertically-Alternating Tiers of Insulative Material and Memory Cells and Methods of Forming a Memory Array

A memory array, comprising:

• vertically alternating tiers of insulative material and memory cells, the memory cells individually comprising:
• a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally oriented for current flow along a first horizontal direction between the first and second source/drain regions;
• and
• a capacitor disposed horizontally relative to the transistor, the capacitor comprising:
• a first electrode electrically coupled to the first source/drain region of the transistor, the first electrode being disposed at an elevation over a substrate equivalent to an elevation over the substrate of the channel region;
• and
• a second electrode horizontally spaced from the second electrode by a capacitor insulator;
• and
• a plurality wordlines, each wordline being disposed above an individual of the channel regions and extending horizontally along a second horizontal direction substantially orthogonal relative to the first horizontal direction.