Ferroelectric tunnel junction memory devices with enhanced read window

A memory device, comprising:

• a first capacitor comprising:
• a first metal structure;
• a second metal structure;
• and
• a ferroelectric film interposed between the first and second metal structures;
• a second capacitor comprising:
• a third metal structure;
• a fourth metal structure;
• and
• a dielectric film interposed between the third and fourth metal structures;
• and
• a transistor comprising:
• a gate;
• a first drain/source;
• and
• a second drain/source;
• wherein the second metal structure is in electrical contact with the gate of the transistor and the third metal structure of the second capacitor.

A method for fabricating a memory device, comprising:

• forming a transistor along a major surface of a substrate, wherein the transistor has a gate, a first drain/source, and a second drain/source;
• and
• forming a plurality of metallization layers over the transistor;
• wherein the step of forming the plurality of metallization layers further comprises:
• forming a first metal structure and a second metal structure with a ferroelectric film interposed therebetween, wherein the second metal structure is in electrical contact with the gate;
• and
• forming a third metal structure and a fourth metal structure with a dielectric film interposed therebetween, wherein the third metal structure is also in electrical contact with the gate, and the fourth metal structure is in electrical contact with the second drain/source.