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US 2023/0403845 A1Published application
Semiconductor structure having tapered bit line
AssigneeNanya Technology Corporation
InventorsPEI-ROU JIANG, CHAO-WEN LAY
Life of this patent
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Abstract
The present disclosure provides a semiconductor structure having a bit line with a tapered configuration. The semiconductor structure includes: a substrate; a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; a polysilicon layer, disposed over the substrate and around the bit line structure; and a landing pad, disposed over the polysilicon layer and the step portion.
Claims19
A semiconductor structure, comprising:
- a substrate;
- a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion;
- a polysilicon layer, disposed over the substrate and around the bit line structure;
- and
- a landing pad, disposed over the polysilicon layer and the step portion.
2 more elements
A semiconductor structure, comprising:
- a substrate;
- a bit line structure, disposed on the substrate and extending in a first direction;
- and
- a polysilicon layer, disposed around a lower portion of the bit line structure, wherein an upper portion of the bit line structure is tapered from the lower portion toward a top surface of the bit line structure.
1 more element
Dependencies are inferred from the claim text.