Memory decision feedback equalizer
AssigneeMicron Technology, Inc.
InventorsJennifer E. Taylor, Raghukiran Sreeramaneni
Life of this patent
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Abstract
A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.
Claims21
(canceled)
A memory device comprising:
- a data (DQ) receiver configured to receive serial data via a bus able to be interconnected to host circuitry;
- and
- a decision feedback equalizer comprising:
- feedback circuitry configured to receive the serial data after the serial data has been corrected of at least some amount of inter-symbol interference;
- a plurality of taps comprising a first tap, a second tap, a third tap, and a fourth tap;
- and
- a plurality of summing circuitry comprising first summing circuitry, second summing circuitry, third summing circuitry, and fourth summing circuitry, wherein each respective summing circuitry of the plurality of summing circuitry is coupled to the feedback circuitry via each respective tap of the plurality of taps, and wherein each respective summing circuitry of the plurality of summing circuitry is operable to receive respective bits of the serial data from the feedback circuitry according to an interleaving pattern implemented by the plurality of taps.
A memory device comprising:
- a data (DQ) receiver configured to receive serial data via a bus able to be interconnected to host circuitry;
- and
- a decision feedback equalizer comprising:
- feedback circuitry configured to receive the serial data after the serial data has been corrected of at least some amount of inter-symbol interference;
- a plurality of taps comprising a first tap, a second tap, a third tap, and a fourth tap;
- and
- a plurality of summing circuitry comprising first summing circuitry, second summing circuitry, third summing circuitry, and fourth summing circuitry, wherein each respective summing circuitry of the plurality of summing circuitry is coupled to the feedback circuitry via each respective tap of the plurality of taps, and wherein each respective summing circuitry of the plurality of summing circuitry is operable to receive respective bits from the feedback circuitry.
A method, comprising:
- receiving a distorted bit;
- receiving an indication of previously transmitted bits;
- adjusting a correction voltage based at least in part on a control signal to control a state of a switchable element and the indication of previously transmitted bits;
- and
- applying the correction voltage to the distorted bit to generate a corrected bit.
Dependencies are inferred from the claim text.