Key generation unit with physical unclonable function, key generator and circuit system

A key generator, comprising:

• a plurality of key generation units, and the plurality of key generator units with a physical unclonable function, wherein each of the plurality of key generation units comprises:
• a multiplexer, electrically connected to one of a plurality of combinational logic circuits in a circuit system, and configured to output a data signal or a scanning series data signal received by the multiplexer based on a scanning enable signal, wherein the data signal is from an output end of the one of the combinational logic circuits;
• a first data flip-flop, electrically connected to the multiplexer, and configured to receive the data signal or the scanning series data signal received by the multiplexer;
• wherein the first data flip-flop outputs the data signal or the scanning series data signal based on an edge of a clock signal being triggered;
• wherein the multiplexer and the first data flip-flop form one of a plurality of scanning flip-flops in the circuit system;
• and
• a second data flip-flop, electrically connected to the one of the combinational logic circuits, and configured to receive a node data signal of a node in the one of the combinational logic circuits;
• wherein when the scanning enable signal is disabled, the second data flip-flop outputs the node data signal as a part of a key based on an edge of a node clock signal being triggered;
• and wherein the node clock signal is the clock signal, or the node clock signal is generated based on the clock signal;
• and
• wherein a first transmission delay time from an input end of the one of the combinational logic circuits to the node of the one of the combinational logic circuits is K times a second transmission delay time from the input end of the combinational logic circuits to the output end of the one of the combinational logic circuits, wherein K is less than 1;
• wherein the one of the combinational logic circuits to which one of the plurality of key generation units is electrically connected is different from another one of the combination logic circuits to which another one of the plurality of key generation units is electrically connected.

A circuit system, comprising:

• a key generator, comprising:
• a plurality of key generation units, and the plurality of key generator units with a physical unclonable function, wherein each of the plurality of key generation units comprises:
• a multiplexer, electrically connected to one of a plurality of combinational logic circuits in a circuit system, and configured to output a data signal or a scanning series data signal received by the multiplexer based on a scanning enable signal, wherein the data signal is from an output end of the one of the combinational logic circuits;
• a first data flip-flop, electrically connected to the multiplexer, and configured to receive the data signal or the scanning series data signal received by the multiplexer;
• wherein the first data flip-flop outputs the data signal or the scanning series data signal based on an edge of a clock signal being triggered;
• wherein the multiplexer and the first data flip-flop form one of a plurality of scanning flip-flops in the circuit system;
• and
• a second data flip-flop, electrically connected to the one of the combinational logic circuits, and configured to receive a node data signal of a node in the one of the combinational logic circuits;
• wherein when the scanning enable signal is disabled, the second data flip-flop outputs the node data signal as a part of a key based on an edge of a node clock signal being triggered;
• and wherein the node clock signal is the clock signal, or the node clock signal is generated based on the clock signal;
• and
• wherein a first transmission delay time from an input end of the one of the combinational logic circuits to the node of the one of the combinational logic circuits is K times a second transmission delay time from the input end of the combinational logic circuits to the output end of the one of the combinational logic circuits, wherein K is less than 1;
• wherein the one of the combinational logic circuits to which one of the plurality of key generation units is electrically connected is different from another one of the combination logic circuits to which another one of the plurality of key generation units is electrically connected;
• the plurality of combinational logic circuits, electrically connected to the plurality of key generation units of the key generator;
• and
• the plurality of scanning flip-flops, electrically connected to the plurality of combinational logic circuits.