US 2023/0403029 A1 · LOW-DENSITY PARITY-CHECK DECODER WITH SCALING TO REDUCE POWER CONSUMPTION

Abstract

A method and apparatus are provided for decoding a plurality of codewords from a received binary bitstream. A first decoding stage processes each of the codewords with a first iterative decoding algorithm based on forward error-correction information of the codewords. A second decoding stage processes selected ones of the codewords with a second iterative decoding algorithm, which is based on forward error-correction information in the selected ones of the codewords. Each codeword selected for the second decoding stage is selected in response to an exit from the decoding of that codeword without the production of a decoded codeword. The second iterative decoding algorithm is configured to enable a greater number of iterations of decoding per codeword than the first iterative decoding algorithm.

Claims14

Dependent claims

A method for decoding a plurality of codewords from a received binary bitstream, comprising:

in a first decoding stage, processing each of the codewords in said plurality with a first iterative decoding algorithm based on forward error-correction information of the codewords;
and
in a second decoding stage, processing selected ones of the codewords of said plurality with a second iterative decoding algorithm based on forward error-correction information in the selected ones of the codewords, wherein:
the selected ones of the codewords are each selected in response to the decoding of one of the codewords, in the first decoding stage, being exited without producing a decoded codeword;
and
the second iterative decoding algorithm has a fixed scaling and is configured to enable a greater number of iterations of decoding per codeword than the first iterative decoding algorithm.

3 more elements

An apparatus, comprising:

a decoder circuit configured to decode codewords using an algorithm performed in decoding iterations;
and
a codeword memory configured to store a portion of the codewords in response to said portion having failed to be decoded by the decoder circuit, in a first decoding stage, after a preset maximum permitted number of the decoding iterations of the algorithm;
wherein the decoder circuit is configured to process codewords of said stored portion in a second decoding stage with a fixed scaling in response to retrieving the codewords of said portion from the codeword memory.

1 more element

Dependencies are inferred from the claim text.

Low-density parity-check decoder with scaling to reduce power consumption

Life of this patent

Low-density parity-check decoder with scaling to reduce power consumption

Life of this patent

Abstract

Claims14