Parallelized decoding of variable-length prefix codes

A system for decoding variable-length codes in a parallel process, the method comprising:

• at least one processor;
• memory in electronic communication with the at least one processor;
• and
• instructions stored in the memory, the instructions being executable by the at least one processor to:
• divide a stream of variable-length code words received as a concatenated bit stream into a series of fixed-length words, each of the fixed-length words comprising at least a portion of an encoded symbol;
• receive, at a first set of decoder circuits, a first fixed-length word and a first prior fixed-length word from the series of fixed-length words, each decoder circuit of the first set of decoder circuits has a respective fixed leftover bit count;
• generate, for each decoder circuit of the first set of decoder circuits, a respective output comprising a decoding result and a new leftover bit-count, each respective output determined based on the first fixed-length word, the first prior fixed-length word, and the respective fixed leftover bit-count;
• generate a set of selected decoder circuit outputs by selecting outputs of the first set of decoder circuits based on a set of first leftover bit-counts of a second set of decoder circuits;
• select one decoder circuit output of the set of selected decoder circuit outputs based on a second leftover bit-count of a third set of decoder circuits;
• and
• output the decoding result and the new leftover bit-count corresponding to the selected one decoder circuit output.

A computer-implemented method for decoding variable-length codes in a parallel process, the computer-implemented method comprising:

• dividing a stream of variable-length code words received at a computing device as a concatenated bit stream into a series of fixed-length words, each of the fixed-length words comprising at least a portion of an encoded symbol;
• receiving, at a first set of decoder circuits, a first fixed length word and a first prior fixed length word from the series of fixed length words, each decoder circuit of the first set of decoder circuits having a respective fixed leftover bit-count;
• generating, by each decoder circuit of the first set of decoder circuits, a respective output comprising a decoding result and a new leftover bit-count, each respective output determined based on the first fixed-length word, the first prior fixed-length word, and the respective fixed leftover bit-count;
• generating a set of selected decoder circuit outputs by selecting outputs of the first set of decoder circuits based on a set of first leftover bit-counts of a second set of decoder circuits;
• selecting one decoder circuit output of the set of selected decoder circuit outputs based on a second leftover bit-count of a third set of decoder circuits;
• and
• outputting the decoding result and the new leftover bit-count corresponding to the selected one decoder circuit output.

A non-transitory computer readable medium storing instructions thereon that, when executed by at least one processor, causes a computing device to:

• divide a stream of variable-length code words received at a computing device as a concatenated bit stream into a series of fixed-length words, each of the fixed-length words comprising at least a portion of an encoded symbol;
• receive, at a first set of decoder circuits, a first fixed length word and a first prior fixed length word from the series of fixed length words, each decoder circuit of the first set of decoder circuits having a respective fixed leftover bit-count;
• generate, by each decoder circuit of the first set of decoder circuits, a respective output comprising a decoding result and a new leftover bit-count, each respective output determined based on the first fixed-length word, the first prior fixed-length word, and the respective fixed leftover bit-count;
• generate a set of selected decoder circuit outputs by selecting outputs of the first set of decoder circuits based on a set of first leftover bit-counts of a second set of decoder circuits;
• select one decoder circuit output of the set of selected decoder circuit outputs based on a second leftover bit-count of a third set of decoder circuits;
• and
• output the decoding result and the new leftover bit-count corresponding to the selected one decoder circuit output.