Phase mixing circuit and multi-phase clock signal alignment circuit including the same

A phase mixing circuit comprising:

• a jitter cancellation circuit configured to mix phases of a first signal input to a first node and a second signal input to a second node to produce a third signal at a third node and a fourth signal at a fourth node;
• and
• a delay adjustment circuit configured to adjust respective delays of the third signal and the fourth signal to produce a fifth signal at a fifth node and a sixth signal at a sixth node,
• wherein the jitter cancellation circuit comprises:
• N+2n inverters connected in series between the first node and the third node;
• N+2n+1 inverters connected in series between the first node and the fourth node;
• N+2n−1 inverters connected in series between the second node and the third node;
• and
• N+2n inverters connected in series between the second node and the fourth node,
• wherein N is an integer greater than or equal to 0 and n is a natural number.

A multi-phase clock signal alignment circuit comprising:

• a plurality of phase delay circuits configured to control delays of a plurality of multi-phase input clock signals to produce a plurality of multi-phase clock signals, respectively;
• a plurality of phase mixing circuits configured to mix phases of the multi-phase clock signals to produce multi-phase output clock signals;
• a clock selection circuit configured to select alpha and beta clock signals from among the multi-phase clock signals or from among the multi-phase output clock signals;
• a first clock delay circuit configurable to provide a first selection clock signal by outputting the alpha clock signal and configurable to provide the first selection clock signal by adjusting a delay, a phase, both of the alpha clock signal;
• a second clock delay circuit configurable to provide a second selection clock signal by outputting the beta clock signal and configurable to provide the second selection clock signal by adjusting a delay, a phase, or both of the beta clock signal;
• a phase detection circuit configured to detect a phase difference between the first selection clock signal and the second selection clock signal;
• and
• a phase control circuit configured to control the delays of the plurality of the phase delay circuits according to an output of the phase detection circuit.