Integrated circuit device

An integrated circuit (IC) device comprising:

• a gate trench formed inside a substrate, the gate trench including a bottom portion and a sidewall portion;
• a gate electrode structure disposed apart from the bottom portion and the sidewall portion of the gate trench inside the gate trench, the gate electrode structure including a gate electrode and a gate capping layer, the gate electrode including a first sub-gate electrode formed in a lower portion of the gate trench and a second sub-gate electrode formed on the first sub-gate electrode, the gate capping layer being formed on the second sub-gate electrode;
• and
• a gate insulating layer formed between the gate trench and the gate electrode structure, the gate insulating layer including a base insulating layer and a reinforcing insulating layer, the base insulating layer being formed between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure, and the reinforcing insulating layer being formed on a sidewall portion of the second sub-gate electrode,
• wherein a second thickness of the gate insulating layer between the sidewall portion of the second sub-gate electrode and the sidewall of the gate trench on a top level of the second sub-gate electrode is greater than a first thickness of the gate insulating layer between the sidewall portion of the gate capping layer and the sidewall portion of the gate trench on a bottom level of the gate capping layer.

An integrated circuit (IC) device comprising:

• a gate trench formed inside a substrate, the gate trench including a bottom portion and a sidewall portion;
• a gate electrode structure disposed apart from the bottom portion and the sidewall portion of the gate trench inside the gate trench, the gate electrode structure including a gate electrode including a first sub-gate electrode formed in a lower portion of the gate trench and including a metal layer, and a second sub-gate electrode formed on the first sub-gate electrode and including a polysilicon layer doped with impurities, and a gate capping layer formed on the second sub-gate electrode;
• and
• a gate insulating layer formed between the gate trench and the gate electrode structure, the gate insulating layer including a liner insulating layer formed on the bottom portion and the sidewall portion of the gate trench and including a silicon oxide layer, a base insulating layer formed between the liner insulating layer and the gate electrode structure, and a reinforcing insulating layer formed on the sidewall portion of the second sub-gate electrode and including a silicon oxide layer,
• wherein a second thickness of the reinforcing insulating layer and the base insulating layer formed on the sidewall portion of the second sub-gate electrode on a top level of the second sub-gate electrode is greater than a first thickness of the base insulating layer formed on the sidewall portion of the gate capping layer on a bottom level of the gate capping layer.