Bump coplanarity for semiconductor device assembly and methods of manufacturing the same

A semiconductor die, comprising:

• a passivation layer including a dielectric layer and a polyimide layer over the dielectric layer;
• a first opening in the passivation layer extending from a surface of the passivation layer through the polyimide layer and partway into, but not completely through, the dielectric layer;
• and
• a first conductive pillar disposed within the opening, the first conductive pillar connected to the bond pad and having a bottom in direct contact with the dielectric layer, the first conductive pillar extending above the surface of the passivation layer.

A method, comprising:

• forming a dielectric layer over a semiconductor die;
• forming a polyimide layer over the dielectric layer;
• exposing the polyimide layer using a reticle including a region configured for a partial exposure;
• developing the exposed polyimide layer, wherein the polyimide layer includes an opening corresponding to the region, and wherein the opening extends from a surface of the polyimide layer partially into, but not completely through, the dielectric layer;
• and
• forming a conductive pillar within the opening, wherein conductive pillar has a bottom in direct contact with the dielectric layer and wherein the conductive pillar is electrically isolated from any circuitry of the semiconductor die.