Hybrid signal and power track for stacked transistors

A semiconductor device comprising:

• a stacked transistor comprising:
• a bottom transistor having one or more bottom source/drain epitaxy regions;
• and
• a top transistor having one or more top source/drain epitaxy regions;
• and
• a plurality of frontside signal lines,
• wherein a bottom source/drain epitaxy region is connected to a first frontside signal line though an interlevel via that is located between cell boundaries of the stacked transistor and an adjacent device.

A method for fabricating a semiconductor device, the method comprising:

• forming a stacked FET, the stacked FET including a top transistor with at least two top source/drain epitaxies and a bottom transistor with at least two bottom source/drain epitaxies;
• forming one or more middle-of-line (MOL) structures;
• forming one or more frontside contacts and frontside vias to wire a first top source/drain epitaxy to a frontside power rail and a second top source/drain epitaxy to a signal line;
• forming one or more BEOL layers;
• and
• forming one or more backside contacts below the bottom source/drain epitaxies, wherein:
• at least one backside contact connects a bottom source/drain epitaxy to a first MOL structure, and
• at least one backside contact connects a bottom source/drain epitaxy to a backside power rail through a backside via.