Method and apparatus for etching a semiconductor substrate in a plasma etch chamber

A method for etching a substrate in a plasma etch chamber, the method comprising:

• forming a plasma from a processing gas containing carbon and at least one halogen;
• exposing a dielectric layer disposed on the substrate to the plasma within the plasma etch chamber;
• and
• applying bias power to an electrode disposed in a substrate support supporting the substrate within the plasma etch chamber while exposed to the plasma during a plurality of macro etch cycles until an end point is reached, each macro etch cycle including a first macro etch period and a second macro etch period, the macro etch period comprises a plurality of micro etch cycles, each micro etch cycle having a bias power on (BPON) period and a bias power off (BPOFF) period, a duration of the BPON period being less than a duration of the BPOFF period, bias power predominantly not applied to the electrode during the second macro etch period, wherein in at least macro etch cycle:
• the BPON period is at least two orders of magnitude shorter in duration than the first macro etch period;
• and
• the BPOFF period is at least two orders of magnitude shorter in duration than the second macro etch period.

A plasma etch chamber comprising

• a chamber body having an interior volume;
• a substrate support disposed in the interior volume of the chamber body, the substrate support configured to retain a substrate thereon during processing, the substrate support having an electrode;
• a bias power control system coupled to the electrode;
• a gas panel configured to provide a processing gas to the interior volume;
• and
• a controller configured to:
• maintain a plasma within the processing chamber formed from the processing gas;
• and
• apply a voltage waveform to the electrode while the substrate disposed on the substrate support is exposed to the plasma during a plurality of macro etch cycles, each macro etch cycle including a first macro etch period and a second macro etch period, the macro etch period comprises a plurality of micro etch cycles, each micro etch cycle having a bias power on (BPON) period and a bias power off (BPOFF) period, a duration of the BPON period being less than a duration of the BPOFF period, and bias power is predominantly not applied to the electrode during the second macro etch period.